From 45d313cd663bc128c86a5208ddb46eef7f7725e5 Mon Sep 17 00:00:00 2001
From: Nick Clifton <nickc@redhat.com>
Date: Fri, 13 Aug 2004 08:14:02 +0000
Subject: [PATCH] O_JSR): Do not allow VECIND addressing for non-SX processors.
---
include/opcode/ChangeLog | 6 ++++++
include/opcode/h8300.h | 2 +-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 684a2e7c462..b8ca4860363 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,9 @@
+2004-08-13 Nick Clifton <nickc@redhat.com>
+
+ PR/301
+ * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
+ processors.
+
2004-08-30 Michal Ludvig <mludvig@suse.cz>
* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
diff --git a/include/opcode/h8300.h b/include/opcode/h8300.h
index 29374df5b4f..fe1097fd286 100644
--- a/include/opcode/h8300.h
+++ b/include/opcode/h8300.h
@@ -1418,7 +1418,7 @@ struct h8_opcode h8_opcodes[] =
{O (O_JSR, SN), AV_H8SX, 0, "jsr", {{ABSJMP | L_32, E}}, {{0x5, 0xD, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}},
{O (O_JSR, SN), AV_H8, 8, "jsr", {{MEMIND, E}}, {{0x5, 0xF, SRC | MEMIND, DATA, E}}},
- {O (O_JSR, SN), AV_H8, 8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}},
+ {O (O_JSR, SN), AV_H8SX, 8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}},
{O (O_LDC, SB), AV_H8, 2, "ldc", {{IMM8, CCR | DST, E}}, {{ 0x0, 0x7, IMM8LIST, E}}},
{O (O_LDC, SB), AV_H8S, 2, "ldc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x7, IMM8LIST, E}}},