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* elf32-arm.c (arm_stub_required_alignment): New.
    (arm_build_one_stub): Use above to partition stubs.
    (make_branch_to_a8_stub): Use arm_stub_a8_veneer_lwm not
    arm_stub_a8_veneer_b_cond.

    ld/testsuite/
    * ld-arm/arm-elf.exp (armelftests): Add cortex-a8-fix-blx-bcond.s.
    * ld-arm/cortex-a8-fix-blx-bcond.s: New.
    * ld-arm/cortex-a8-fix-blx-bcond.d: New.
This commit is contained in:
Julian Brown
2010-08-25 12:37:30 +00:00
parent 6f0341784b
commit 4563a86028
6 changed files with 1238 additions and 4 deletions
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6
ld/testsuite/ChangeLog
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@ -1,3 +1,9 @@
2010-08-25 Julian Brown <julian@codesourcery.com>
* ld-arm/arm-elf.exp (armelftests): Add cortex-a8-fix-blx-bcond.s.
* ld-arm/cortex-a8-fix-blx-bcond.s: New.
* ld-arm/cortex-a8-fix-blx-bcond.d: New.
2010-08-24 H.J. Lu <hongjiu.lu@intel.com>
* ld-x86-64/x86-64.exp: Fix typos.

4
ld/testsuite/ld-arm/arm-elf.exp
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@ -221,6 +221,10 @@ set armelftests {
"-EL -mcpu=cortex-a8" {cortex-a8-fix-hdr.s}
{{objdump -dr cortex-a8-fix-hdr.d}}
"cortex-a8-fix-hdr"}
{"Cortex-A8 erratum fix, blx.w and b<cond>.w together"
"-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-blx-bcond.s}
{{objdump -dr cortex-a8-fix-blx-bcond.d}}
"cortex-a8-fix-blx-bcond"}
{"Unwinding and -gc-sections" "-gc-sections" "" {gc-unwind.s}
{{objdump -sj.data gc-unwind.d}}
"gc-unwind"}

1107
ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.d Normal file
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81
ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.s Normal file
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@ -0,0 +1,81 @@
.syntax unified
.cpu cortex-a8
.thumb
.text
@ expansion 32 bytes
.macro bw1
1:
add.w r0, r1, r2
blx.w arm_target
add.w r0, r1, r2
blx.w arm_target
add.w r0, r1, r2
blx.w arm_target
add.w r0, r1, r2
blx.w arm_target
.endm
@ expansion 128 bytes
.macro bw2
bw1
bw1
bw1
bw1
.endm
@ expansion 32 bytes
.macro bw3
1:
add.w r0, r1, r2
bne.w 1b
add.w r0, r1, r2
bne.w 1b
add.w r0, r1, r2
bne.w 1b
add.w r0, r1, r2
bne.w 1b
.endm
@ expansion 128 bytes
.macro bw4
bw3
bw3
bw3
bw3
.endm
.align 3
.global _start
.thumb
.thumb_func
.type _start, %function
_start:
nop
@ Trigger Cortex-A8 erratum workaround with b<cond> instructions.
bw4
bw4
nop
.rept 957
nop.w
.endr
.arm
arm_target:
add r3, r4, r5
bx lr
.thumb
bl_insns:
nop
@ ...and again with bl instructions.
bw2
bw2
bx lr