diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index dcde282527f..355a162b0ec 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2017-05-01 Michael Clark + + * riscv-opc.c (riscv_opcodes) : Use RA not T1 as a temporary + register. + 2017-05-02 Maciej W. Rozycki * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index c629d2f4ccd..0188a653f20 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -147,7 +147,7 @@ const struct riscv_opcode riscv_opcodes[] = {"jal", "32C", "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS }, {"jal", "I", "a", MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS }, {"call", "I", "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, -{"call", "I", "c", (X_T1 << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO }, +{"call", "I", "c", (X_RA << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO }, {"tail", "I", "c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, {"jump", "I", "c,s", 0, (int) M_CALL, match_never, INSN_MACRO }, {"nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS },