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RISC-V: Cache management instructions
This commit adds 'Zicbom' / 'Zicboz' instructions. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add handling for new instruction classes. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN, MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL, MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros. * opcode/riscv.h (enum riscv_insn_class): Add new instruction classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add cache-block management instructions.
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@ -2036,6 +2036,15 @@
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#define MASK_PREFETCH_R 0x1f07fff
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#define MATCH_PREFETCH_W 0x306013
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#define MASK_PREFETCH_W 0x1f07fff
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/* Zicbom/Zicboz instructions. */
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#define MATCH_CBO_CLEAN 0x10200f
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#define MASK_CBO_CLEAN 0xfff07fff
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#define MATCH_CBO_FLUSH 0x20200f
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#define MASK_CBO_FLUSH 0xfff07fff
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#define MATCH_CBO_INVAL 0x200f
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#define MASK_CBO_INVAL 0xfff07fff
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#define MATCH_CBO_ZERO 0x40200f
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#define MASK_CBO_ZERO 0xfff07fff
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/* Unprivileged Counter/Timers CSR addresses. */
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#define CSR_CYCLE 0xc00
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#define CSR_TIME 0xc01
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