RISC-V: Cache management instructions

This commit adds 'Zicbom' / 'Zicboz' instructions.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
	new instruction classes.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN,
	MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL,
	MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros.
	* opcode/riscv.h (enum riscv_insn_class): Add new instruction
	classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add cache-block management
	instructions.
This commit is contained in:
Tsukasa OI
2022-01-11 19:14:02 +09:00
committed by Nelson Chu
parent 3b374308d3
commit 41d6ac5da6
14 changed files with 93 additions and 0 deletions

View File

@ -2036,6 +2036,15 @@
#define MASK_PREFETCH_R 0x1f07fff
#define MATCH_PREFETCH_W 0x306013
#define MASK_PREFETCH_W 0x1f07fff
/* Zicbom/Zicboz instructions. */
#define MATCH_CBO_CLEAN 0x10200f
#define MASK_CBO_CLEAN 0xfff07fff
#define MATCH_CBO_FLUSH 0x20200f
#define MASK_CBO_FLUSH 0xfff07fff
#define MATCH_CBO_INVAL 0x200f
#define MASK_CBO_INVAL 0xfff07fff
#define MATCH_CBO_ZERO 0x40200f
#define MASK_CBO_ZERO 0xfff07fff
/* Unprivileged Counter/Timers CSR addresses. */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01