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Add load-link, store-conditional paired EVA instructions

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Add paired load-link and store-conditional instructions to the
EVA ASE for MIPS32R6[1].  These instructions are optional within
the EVA ASE.  Their presence is indicated by the XNP bit in the
Config5 register.

[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
     Instruction Set Manual", Imagination Technologies Ltd., Document
     Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
     "Alphabetical List of Instructions", pp. 230-231, pp. 357-360.

gas/
	* config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.
	(macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.
	(mips_after_parse_args): Translate EVA to EVA_R6.
	* testsuite/gas/mips/ase-errors-1.s: Add new instructions.
	* testsuite/gas/mips/eva.s: Likewise.
	* testsuite/gas/mips/ase-errors-1.l: Check errors for
	 new instructions.
	* testsuite/gas/mips/mipsr6@eva.d: Check new test cases.

include/
	* opcode/mips.h (ASE_EVA_R6): New macro.
	(M_LLWPE_AB, M_SCWPE_AB): New enum values.

opcodes/
	* mips-dis.c (mips_calculate_combination_ases): Add ISA
	argument and set ASE_EVA_R6 appropriately.
	(set_default_mips_dis_options): Pass ISA to above.
	(parse_mips_dis_option): Likewise.
	* mips-opc.c (EVAR6): New macro.
	(mips_builtin_opcodes): Add llwpe, scwpe.

Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>
This commit is contained in:
Faraz Shahbazker
2019-04-28 18:21:00 -07:00
parent be0d3bbbcd
commit 41cee0897b
11 changed files with 124 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
include/opcode/mips.h
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@ -1308,6 +1308,9 @@ static const unsigned int mips_isa_table[] = {
#define ASE_LOONGSON_EXT 0x00800000
/* Loongson EXTensions R2 (EXT2) instructions. */
#define ASE_LOONGSON_EXT2 0x01000000
/* The Enhanced VA Scheme (EVA) extension has instructions which are
only valid for the R6 ISA. */
#define ASE_EVA_R6 0x02000000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@ -1631,6 +1634,7 @@ enum
M_LLDP_AB,
M_LLE_AB,
M_LLWP_AB,
M_LLWPE_AB,
M_LQ_AB,
M_LW_AB,
M_LWE_AB,
@ -1684,6 +1688,7 @@ enum
M_SCDP_AB,
M_SCE_AB,
M_SCWP_AB,
M_SCWPE_AB,
M_SD_AB,
M_SDC1_AB,
M_SDC2_AB,