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[PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction

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This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/dc-data-cache-operation-an-alias-of-sys)

This patch adds the DC CVADP instruction. Since this has a separate
identification mechanism a new feature bit is added.

*** include/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_CVADP): New.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
	(aarch64_sys_ins_reg_supported_p): New check for above.

*** gas/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* testsuite/gas/aarch64/sysreg-4.s: Test instruction.
	* testsuite/gas/aarch64/sysreg-4.d: Likewise.
	* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
This commit is contained in:
Sudakshina Das
2018-09-26 10:54:07 +01:00
committed by Richard Earnshaw
parent 2ac435d466
commit 3fd229a447
8 changed files with 28 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
gas/ChangeLog
View File

@ -1,3 +1,9 @@
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test instruction.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
2018-10-09 Sudakshina Das <sudi.das@arm.com> 2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New. * config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New.

1
gas/testsuite/gas/aarch64/illegal-sysreg-4.l
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@ -5,3 +5,4 @@
[^:]*:[0-9]+: Error: selected processor does not support `dvp rctx,x2' [^:]*:[0-9]+: Error: selected processor does not support `dvp rctx,x2'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx' [^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
[^:]*:[0-9]+: Error: selected processor does not support `cpp rctx,x3' [^:]*:[0-9]+: Error: selected processor does not support `cpp rctx,x3'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'cvadp'

1
gas/testsuite/gas/aarch64/sysreg-4.d
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@ -10,3 +10,4 @@ Disassembly of section \.text:
.*: d50b7381 cfp rctx, x1 .*: d50b7381 cfp rctx, x1
.*: d50b73a2 dvp rctx, x2 .*: d50b73a2 dvp rctx, x2
.*: d50b73e3 cpp rctx, x3 .*: d50b73e3 cpp rctx, x3
.*: d50b7d24 dc cvadp, x4

1
gas/testsuite/gas/aarch64/sysreg-4.s
View File

@ -3,3 +3,4 @@ func:
cfp rctx, x1 cfp rctx, x1
dvp rctx, x2 dvp rctx, x2
cpp rctx, x3 cpp rctx, x3
dc cvadp, x4

4
include/ChangeLog
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@ -1,3 +1,7 @@
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_CVADP): New.
2018-10-09 Sudakshina Das <sudi.das@arm.com> 2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New. * opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.

5
include/opcode/aarch64.h
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@ -72,6 +72,8 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_SB 0x10000000000ULL #define AARCH64_FEATURE_SB 0x10000000000ULL
/* Execution and Data Prediction Restriction instructions. */ /* Execution and Data Prediction Restriction instructions. */
#define AARCH64_FEATURE_PREDRES 0x20000000000ULL #define AARCH64_FEATURE_PREDRES 0x20000000000ULL
/* DC CVADP. */
#define AARCH64_FEATURE_CVADP 0x40000000000ULL
/* Architectures are the sum of the base and extensions. */ /* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
@ -100,7 +102,8 @@ typedef uint32_t aarch64_insn;
| AARCH64_FEATURE_FLAGMANIP \ | AARCH64_FEATURE_FLAGMANIP \
| AARCH64_FEATURE_FRINTTS \ | AARCH64_FEATURE_FRINTTS \
| AARCH64_FEATURE_SB \ | AARCH64_FEATURE_SB \
| AARCH64_FEATURE_PREDRES) | AARCH64_FEATURE_PREDRES \
| AARCH64_FEATURE_CVADP)
#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
(aarch64_sys_ins_reg_supported_p): New check for above.
2018-10-09 Sudakshina Das <sudi.das@arm.com> 2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-dis.c (aarch64_ext_sysins_op): Add case for * aarch64-dis.c (aarch64_ext_sysins_op): Add case for

6
opcodes/aarch64-opc.c
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@ -4349,6 +4349,7 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
{ "csw", CPENS (0, C7, C10, 2), F_HASXT }, { "csw", CPENS (0, C7, C10, 2), F_HASXT },
{ "cvau", CPENS (3, C7, C11, 1), F_HASXT }, { "cvau", CPENS (3, C7, C11, 1), F_HASXT },
{ "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT }, { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
{ "cvadp", CPENS (3, C7, C13, 1), F_HASXT | F_ARCHEXT },
{ "civac", CPENS (3, C7, C14, 1), F_HASXT }, { "civac", CPENS (3, C7, C14, 1), F_HASXT },
{ "cisw", CPENS (0, C7, C14, 2), F_HASXT }, { "cisw", CPENS (0, C7, C14, 2), F_HASXT },
{ 0, CPENS(0,0,0,0), 0 } { 0, CPENS(0,0,0,0), 0 }
@ -4488,6 +4489,11 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2)) && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
return FALSE; return FALSE;
/* DC CVADP. Values are from aarch64_sys_regs_dc. */
if (reg->value == CPENS (3, C7, C13, 1)
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
return FALSE;
/* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */ /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
if ((reg->value == CPENS (0, C7, C9, 0) if ((reg->value == CPENS (0, C7, C9, 0)
|| reg->value == CPENS (0, C7, C9, 1)) || reg->value == CPENS (0, C7, C9, 1))