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https://github.com/espressif/binutils-gdb.git
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* Monster patch - may destablize MIPS sims for a little while.
* Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904
This commit is contained in:
Frank Ch. Eigler
@ -561,7 +561,6 @@ struct _sim_cpu {
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/* start-sanitize-sky */
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#ifdef TARGET_SKY
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#ifndef TM_TXVU_H
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/* Number of machine registers */
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#define NUM_VU_REGS 153
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#define NUM_VU_INTEGER_REGS 16
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@ -574,7 +573,8 @@ struct _sim_cpu {
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#undef NUM_REGS
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#define NUM_REGS (NUM_R5900_REGS + 2*(NUM_VU_REGS) + 2*(NUM_VIF_REGS))
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#endif /* no tm-txvu.h */
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#endif
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#endif /* TARGET_SKY */
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/* end-sanitize-sky */
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enum float_operation
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/* start-sanitize-sky */
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@ -665,7 +665,6 @@ enum float_operation
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hilo_history lo_history;
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#define LOHISTORY (&(CPU)->lo_history)
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/* start-sanitize-r5900 */
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sim_r5900_cpu r5900;
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@ -675,7 +674,13 @@ enum float_operation
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/* The MDMX ISA has a very very large accumulator */
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unsigned8 acc[3 * 8];
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/* end-sanitize-vr5400 */
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/* start-sanitize-sky */
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#ifdef TARGET_SKY
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/* Device on which instruction issue last occured. */
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char cur_device;
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#endif
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/* end-sanitize-sky */
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sim_cpu_base base;
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};
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@ -709,7 +714,7 @@ struct sim_state {
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/* Record of option for floating point implementation type. */
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int fp_type_opt;
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#define STATE_FP_TYPE_OPT(sd) ((sd)->fp_type_opt)
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#define STATE_FP_TYPE_OPT_TARGET 0x80000000
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#define STATE_FP_TYPE_OPT_ACCURATE 0x80000000
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#endif
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#endif
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/* end-sanitize-sky */
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@ -746,7 +751,29 @@ struct sim_state {
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#define status_CU2 (1 << 30) /* COP2 usable */
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/* end-sanitize-r5900 */
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#define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */
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/* Specializations for TX39 family */
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#define status_IEc (1 << 0) /* Interrupt enable (current) */
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#define status_KUc (1 << 1) /* Kernel/User mode */
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#define status_IEp (1 << 2) /* Interrupt enable (previous) */
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#define status_KUp (1 << 3) /* Kernel/User mode */
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#define status_IEo (1 << 4) /* Interrupt enable (old) */
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#define status_KUo (1 << 5) /* Kernel/User mode */
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#define status_IM_mask (0xff) /* Interrupt mask */
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#define status_IM_shift (8)
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#define status_NMI (1 << 20) /* NMI */
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#define status_NMI (1 << 20) /* NMI */
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#define cause_EXC_mask (0x1f) /* Exception code */
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#define cause_EXC_shift (2)
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#define cause_SW0 (1 << 8) /* Software interrupt 0 */
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#define cause_SW1 (1 << 9) /* Software interrupt 1 */
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#define cause_IP_mask (0x3f) /* Interrupt pending field */
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#define cause_IP_shift (10)
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#define cause_CE_mask (0x3) /* Coprocessor error */
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#define cause_CE_shift (28)
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#define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */
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/* NOTE: We keep the following status flags as bit values (1 for true,
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0 for false). This allows them to be used in binary boolean
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@ -754,7 +781,11 @@ struct sim_state {
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value is. */
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/* UserMode */
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#ifdef SUBTARGET_R3900
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#define UserMode ((SR & status_KUc) ? 1 : 0)
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#else
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#define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
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#endif /* SUBTARGET_R3900 */
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/* BigEndianMem */
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/* Hardware configuration. Affects endianness of LoadMemory and
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@ -799,6 +830,8 @@ struct sim_state {
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#define FPE (15)
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#define DebugBreakPoint (16)
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#define Watch (23)
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#define NMIReset (31)
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/* The following exception code is actually private to the simulator
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world. It is *NOT* a processor feature, and is used to signal
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@ -807,7 +840,7 @@ struct sim_state {
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void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
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#define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction))
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#define SignalExceptionInterrupt() signal_exception (SD, CPU, NULL_CIA, Interrupt)
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#define SignalExceptionInterrupt() signal_exception (SD, CPU, cia, Interrupt)
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#define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch)
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#define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore)
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#define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad)
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@ -815,7 +848,7 @@ void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exceptio
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#define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE)
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#define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow)
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#define SignalExceptionCoProcessorUnusable() signal_exception (SD, CPU, cia, CoProcessorUnusable)
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#define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset)
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/* Co-processor accesses */
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@ -931,6 +964,38 @@ INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_
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char* pr_addr PARAMS ((SIM_ADDR addr));
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char* pr_uword64 PARAMS ((uword64 addr));
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/* start-sanitize-sky */
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#ifdef TARGET_SKY
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#ifdef SIM_ENGINE_HALT_HOOK
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#undef SIM_ENGINE_HALT_HOOK
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#endif
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void sky_sim_engine_halt PARAMS ((SIM_DESC sd, sim_cpu *last, sim_cia cia));
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#define SIM_ENGINE_HALT_HOOK(sd, last, cia) sky_sim_engine_halt(sd, last, cia);
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#ifndef TM_TXVU_H /* In case GDB hasn't been configured yet */
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enum txvu_cpu_context
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{
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TXVU_CPU_AUTO = -1, /* context-sensitive context */
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TXVU_CPU_MASTER, /* R5900 core */
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TXVU_CPU_VU0, /* Vector units */
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TXVU_CPU_VU1,
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TXVU_CPU_VIF0, /* FIFO's */
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TXVU_CPU_VIF1,
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TXVU_CPU_LAST /* Count of context types */
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};
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/* memory segment for communication with GDB */
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#define GDB_COMM_AREA 0x21010000
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#define GDB_COMM_SIZE 0x4000
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/* Memory address containing last device to execute */
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#define LAST_DEVICE GDB_COMM_AREA
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#define BREAK_MASK 0x02 /* Breakpoint bit is #57 */
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#endif /* !TM_TXVU_H */
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#endif /* TARGET_SKY */
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/* end-sanitize-sky */
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#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
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#include "sim-main.c"
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