espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-20 18:08:24 +08:00
Code Issues Packages Projects Releases Wiki Activity

[AArch64] Add ARMv8.3 combined pointer authentication load instructions

Browse Source 
Add support for ARMv8.3 LDRAA and LDRAB combined pointer authentication and
load instructions.

These instructions authenticate the base register and load 8 byte from it plus
a scaled 10-bit offset with optional writeback to update the base register.

A new instruction class (ldst_imm10) and operand type (AARCH64_OPND_ADDR_SIMM10)
were introduced to handle the special addressing form.

include/
2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
	(enum aarch64_insn_class): Add ldst_imm10.

opcodes/
2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* aarch64-tbl.h (QL_X1NIL): New.
	(arch64_opcode_table): Add ldraa, ldrab.
	(AARCH64_OPERANDS): Add "ADDR_SIMM10".
	* aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
	* aarch64-asm.c (aarch64_ins_addr_simm10): Define.
	* aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
	* aarch64-dis.c (aarch64_ext_addr_simm10): Define.
	* aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
	* aarch64-opc.c (fields): Add data for FLD_S_simm10.
	(operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
	(aarch64_print_operand): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

gas/
2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_ADDR_SIMM10.
	(fix_insn): Likewise.
	(warn_unpredictable_ldst): Handle ldst_imm10.
	* testsuite/gas/aarch64/pac.s: Add ldraa and ldrab tests.
	* testsuite/gas/aarch64/pac.d: Likewise.
	* testsuite/gas/aarch64/illegal-ldraa.s: New.
	* testsuite/gas/aarch64/illegal-ldraa.l: New.
	* testsuite/gas/aarch64/illegal-ldraa.d: New.
This commit is contained in:
Szabolcs Nagy
2016-11-18 09:49:06 +00:00
parent 6ec49e7c0a
commit 3f06e55061
20 changed files with 1822 additions and 1530 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/opcode/aarch64.h
View File

@ -225,6 +225,7 @@ enum aarch64_opnd
friendly feature of using LDR/STR as the
the mnemonic name for LDUR/STUR instructions
wherever there is no ambiguity. */
AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
@ -465,6 +466,7 @@ enum aarch64_insn_class
ldst_immpost,
ldst_immpre,
ldst_imm9, /* immpost or immpre */
ldst_imm10, /* LDRAA/LDRAB */
ldst_pos,
ldst_regoff,
ldst_unpriv,