espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-08-06 14:49:38 +08:00
Code Issues Packages Projects Releases Wiki Activity

This is a series of patches that add support for the SPARC M7 cpu to

Browse Source 
binutils.  They were discussed and approved here:

  https://sourceware.org/ml/binutils/2014-10/msg00038.html
This commit is contained in:
Jose E. Marchesi
2014-10-09 13:16:53 +01:00
committed by Nick Clifton
parent fcbdedf866
commit 3d68f91c0f
26 changed files with 2036 additions and 1378 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
include/opcode/sparc.h
View File

@ -100,6 +100,7 @@ typedef struct sparc_opcode
/* This was called "delayed" in versions before the flags. */
unsigned int flags;
unsigned int hwcaps;
unsigned int hwcaps2;
short architecture; /* Bitmask of sparc_opcode_arch_val's. */
} sparc_opcode;
@ -115,7 +116,8 @@ typedef struct sparc_opcode
#define F_PREF_ALIAS (F_ALIAS|F_PREFERRED)
/* These must match the HWCAP_* values precisely. */
/* These must match the ELF_SPARC_HWCAP_* and ELF_SPARC_HWCAP2_*
values precisely. See include/elf/sparc.h. */
#define HWCAP_MUL32 0x00000001 /* umul/umulcc/smul/smulcc insns */
#define HWCAP_DIV32 0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
#define HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */
@ -148,6 +150,20 @@ typedef struct sparc_opcode
#define HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */
#define HWCAP_CRC32C 0x20000000 /* CRC32C insn */
#define HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */
#define HWCAP2_VIS3B 0x00000002 /* VIS3 present on multiple chips */
#define HWCAP2_ADP 0x00000004 /* Application Data Protection */
#define HWCAP2_SPARC5 0x00000008 /* The 29 new fp and sub instructions */
#define HWCAP2_MWAIT 0x00000010 /* mwait instruction and load/monitor ASIs */
#define HWCAP2_XMPMUL 0x00000020 /* XOR multiple precision multiply */
#define HWCAP2_XMONT 0x00000040 /* XOR Montgomery mult/sqr instructions */
#define HWCAP2_NSEC \
0x00000080 /* pause insn with support for nsec timings */
#define HWCAP2_FJATHHPC 0x00001000 /* Fujitsu HPC instrs */
#define HWCAP2_FJDES 0x00002000 /* Fujitsu DES instrs */
#define HWCAP2_FJAES 0x00010000 /* Fujitsu AES instrs */
/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
macro), which is 64 bits. It is handled as a special case.
@ -173,6 +189,7 @@ typedef struct sparc_opcode
g frsd floating point register.
H frsd floating point register (double/even).
J frsd floating point register (quad/multiple of 4).
} frsd floating point register (double/even) that is == frs2
b crs1 coprocessor register
c crs2 coprocessor register
D crsd coprocessor register
@ -214,6 +231,7 @@ typedef struct sparc_opcode
s %fprs. (v9)
P %pc. (v9)
W %tick. (v9)
{ %mcdper. (v9b)
o %asi. (v9)
6 %fcc0. (v9)
7 %fcc1. (v9)