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MIPS16/opcodes: Fix off-by-one indentation in `print_mips16_insn_arg'

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opcodes/
	* mips-dis.c (print_mips16_insn_arg): Remove extraneous
	indentation space across.
This commit is contained in:
Maciej W. Rozycki
2016-12-08 23:29:37 +00:00
parent 860b03a8f3
commit 39f66f3ae2
2 changed files with 34 additions and 29 deletions
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5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
* mips-dis.c (print_mips16_insn_arg): Remove extraneous
indentation space across.
2016-12-08 Maciej W. Rozycki <macro@imgtec.com> 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
* mips-dis.c (print_mips16_insn_arg): Avoid delay-slot * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot

58
opcodes/mips-dis.c
View File

@ -1914,36 +1914,36 @@ print_mips16_insn_arg (struct disassemble_info *info,
if (!pcrel_op->include_isa_bit && use_extend) if (!pcrel_op->include_isa_bit && use_extend)
baseaddr = memaddr - 2; baseaddr = memaddr - 2;
else if (!pcrel_op->include_isa_bit) else if (!pcrel_op->include_isa_bit)
{ {
bfd_byte buffer[2]; bfd_byte buffer[2];
/* If this instruction is in the delay slot of a JAL/JALX /* If this instruction is in the delay slot of a JAL/JALX
instruction, the base address is the address of the instruction, the base address is the address of the
JAL/JALX instruction. If it is in the delay slot of JAL/JALX instruction. If it is in the delay slot of
a JR/JALR instruction, the base address is the address a JR/JALR instruction, the base address is the address
of the JR/JALR instruction. This test is unreliable: of the JR/JALR instruction. This test is unreliable:
we have no way of knowing whether the previous word is we have no way of knowing whether the previous word is
instruction or data. */ instruction or data. */
if (info->read_memory_func (memaddr - 4, buffer, 2, info) == 0 if (info->read_memory_func (memaddr - 4, buffer, 2, info) == 0
&& (((info->endian == BFD_ENDIAN_BIG && (((info->endian == BFD_ENDIAN_BIG
? bfd_getb16 (buffer) ? bfd_getb16 (buffer)
: bfd_getl16 (buffer)) : bfd_getl16 (buffer))
& 0xf800) == 0x1800)) & 0xf800) == 0x1800))
baseaddr = memaddr - 4; baseaddr = memaddr - 4;
else if (info->read_memory_func (memaddr - 2, buffer, 2, else if (info->read_memory_func (memaddr - 2, buffer, 2,
info) == 0 info) == 0
&& (((info->endian == BFD_ENDIAN_BIG && (((info->endian == BFD_ENDIAN_BIG
? bfd_getb16 (buffer) ? bfd_getb16 (buffer)
: bfd_getl16 (buffer)) : bfd_getl16 (buffer))
& 0xf89f) == 0xe800) & 0xf89f) == 0xe800)
&& (((info->endian == BFD_ENDIAN_BIG && (((info->endian == BFD_ENDIAN_BIG
? bfd_getb16 (buffer) ? bfd_getb16 (buffer)
: bfd_getl16 (buffer)) : bfd_getl16 (buffer))
& 0x0060) != 0x0060)) & 0x0060) != 0x0060))
baseaddr = memaddr - 2; baseaddr = memaddr - 2;
else else
baseaddr = memaddr; baseaddr = memaddr;
} }
} }
print_insn_arg (info, state, opcode, operand, baseaddr + 1, uval); print_insn_arg (info, state, opcode, operand, baseaddr + 1, uval);