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gas/
2004-11-25 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (optimize_imm): Adjust immediates to only those permissible for the selected instruction suffix. (process_suffix): For DefaultSize instructions, suppressing the guessing of a 'q' suffix if the instruction doesn't support it is pointless, because only an 'l' suffix can be guessed in this place. gas/testsuite/ 2004-11-25 Jan Beulich <jbeulich@novell.com> * gas/i386/x86-64-inval.[sl]: Remove sahf/lahf. include/opcode/ 2004-11-25 Jan Beulich <jbeulich@novell.com> * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves to/from test registers are illegal in 64-bit mode. Add missing NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix (previously one had to explicitly encode a rex64 prefix). Re-enable lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
This commit is contained in:
Jan Beulich
@ -1,3 +1,11 @@
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2004-11-25 Jan Beulich <jbeulich@novell.com>
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* config/tc-i386.c (optimize_imm): Adjust immediates to only those
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permissible for the selected instruction suffix.
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(process_suffix): For DefaultSize instructions, suppressing the
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guessing of a 'q' suffix if the instruction doesn't support it is
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pointless, because only an 'l' suffix can be guessed in this place.
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2004-11-24 Nick Clifton <nickc@redhat.com>
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* config/tc-iq2000.c: Remove support for IQ10 processor.
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@ -2362,9 +2362,6 @@ process_suffix (void)
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&& (i.tm.opcode_modifier & No_sSuf))
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{
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i.suffix = stackop_size;
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if (i.suffix == QWORD_MNEM_SUFFIX
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&& (i.tm.opcode_modifier & No_qSuf))
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i.suffix = LONG_MNEM_SUFFIX;
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}
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else if (intel_syntax
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&& !i.suffix
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@ -2702,7 +2699,7 @@ finalize_imm ()
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i.types[0] = overlap0;
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overlap1 = i.types[1] & i.tm.operand_types[1];
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if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
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if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
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&& overlap1 != Imm8 && overlap1 != Imm8S
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&& overlap1 != Imm16 && overlap1 != Imm32S
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&& overlap1 != Imm32 && overlap1 != Imm64)
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@ -1,3 +1,6 @@
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2004-11-25 Jan Beulich <jbeulich@novell.com>
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* gas/i386/x86-64-inval.[sl]: Remove sahf/lahf.
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2004-11-24 Paul Brook <paul@codesourcery.com>
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* gas/elf/group0a.d: Adjust expected secion ordering.
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@ -48,8 +48,6 @@
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.*:49: Error: .*
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.*:50: Error: .*
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.*:51: Error: .*
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.*:52: Error: .*
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.*:53: Error: .*
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GAS LISTING .*
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@ -75,34 +73,32 @@ GAS LISTING .*
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20 [ ]*foo:[ ]*jcxz foo # No prefix exists to select CX as a counter
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21 [ ]*jmpl \*%eax # 32-bit data size not allowed
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22 [ ]*jmpl \*\(%rax\) # 32-bit data size not allowed
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23 [ ]*lahf # illegal
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24 [ ]*lcalll \$0,\$0 # illegal
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25 [ ]*lcallq \$0,\$0 # illegal
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26 [ ]*ldsl %eax,\(%rax\) # illegal
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27 [ ]*ldsq %rax,\(%rax\) # illegal
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28 [ ]*lesl %eax,\(%rax\) # illegal
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29 [ ]*lesq %rax,\(%rax\) # illegal
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30 [ ]*ljmpl \$0,\$0 # illegal
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31 [ ]*ljmpq \$0,\$0 # illegal
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32 [ ]*ljmpq \*\(%rax\) # 64-bit data size not allowed
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33 [ ]*loopw foo # No prefix exists to select CX as a counter
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34 [ ]*loopew foo # No prefix exists to select CX as a counter
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35 [ ]*loopnew foo # No prefix exists to select CX as a counter
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36 [ ]*loopnzw foo # No prefix exists to select CX as a counter
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37 [ ]*loopzw foo # No prefix exists to select CX as a counter
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38 [ ]*leavel # can't have 32-bit stack operands
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39 [ ]*pop %ds # illegal
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40 [ ]*pop %es # illegal
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41 [ ]*pop %ss # illegal
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42 [ ]*popa # illegal
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43 [ ]*popl %eax # can't have 32-bit stack operands
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44 [ ]*push %cs # illegal
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45 [ ]*push %ds # illegal
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46 [ ]*push %es # illegal
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47 [ ]*push %ss # illegal
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48 [ ]*pusha # illegal
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49 [ ]*pushl %eax # can't have 32-bit stack operands
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50 [ ]*pushfl # can't have 32-bit stack operands
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51 [ ]*popfl # can't have 32-bit stack operands
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52 [ ]*retl # can't have 32-bit stack operands
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53 [ ]*sahf # illegal
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23 [ ]*lcalll \$0,\$0 # illegal
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24 [ ]*lcallq \$0,\$0 # illegal
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25 [ ]*ldsl %eax,\(%rax\) # illegal
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26 [ ]*ldsq %rax,\(%rax\) # illegal
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27 [ ]*lesl %eax,\(%rax\) # illegal
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28 [ ]*lesq %rax,\(%rax\) # illegal
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29 [ ]*ljmpl \$0,\$0 # illegal
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30 [ ]*ljmpq \$0,\$0 # illegal
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31 [ ]*ljmpq \*\(%rax\) # 64-bit data size not allowed
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32 [ ]*loopw foo # No prefix exists to select CX as a counter
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33 [ ]*loopew foo # No prefix exists to select CX as a counter
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34 [ ]*loopnew foo # No prefix exists to select CX as a counter
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35 [ ]*loopnzw foo # No prefix exists to select CX as a counter
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36 [ ]*loopzw foo # No prefix exists to select CX as a counter
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37 [ ]*leavel # can't have 32-bit stack operands
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38 [ ]*pop %ds # illegal
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39 [ ]*pop %es # illegal
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40 [ ]*pop %ss # illegal
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41 [ ]*popa # illegal
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42 [ ]*popl %eax # can't have 32-bit stack operands
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43 [ ]*push %cs # illegal
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44 [ ]*push %ds # illegal
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45 [ ]*push %es # illegal
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46 [ ]*push %ss # illegal
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47 [ ]*pusha # illegal
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48 [ ]*pushl %eax # can't have 32-bit stack operands
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49 [ ]*pushfl # can't have 32-bit stack operands
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50 [ ]*popfl # can't have 32-bit stack operands
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51 [ ]*retl # can't have 32-bit stack operands
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@ -20,7 +20,6 @@
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foo: jcxz foo # No prefix exists to select CX as a counter
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jmpl *%eax # 32-bit data size not allowed
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jmpl *(%rax) # 32-bit data size not allowed
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lahf # illegal
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lcalll $0,$0 # illegal
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lcallq $0,$0 # illegal
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ldsl %eax,(%rax) # illegal
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@ -50,4 +49,3 @@ foo: jcxz foo # No prefix exists to select CX as a counter
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pushfl # can't have 32-bit stack operands
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popfl # can't have 32-bit stack operands
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retl # can't have 32-bit stack operands
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sahf # illegal
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@ -1,3 +1,12 @@
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2004-11-25 Jan Beulich <jbeulich@novell.com>
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* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
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to/from test registers are illegal in 64-bit mode. Add missing
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NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
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(previously one had to explicitly encode a rex64 prefix). Re-enable
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lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
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support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
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2004-11-23 Jan Beulich <jbeulich@novell.com>
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* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
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@ -85,7 +85,7 @@ static const template i386_optab[] =
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#define MOV_AX_DISP32 0xa0
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/* In the 64bit mode the short form mov immediate is redefined to have
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64bit displacement value. */
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{ "mov", 2, 0xa0, X, CpuNo64,bwlq_Suf|D|W, { Disp16|Disp32, Acc, 0 } },
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{ "mov", 2, 0xa0, X, CpuNo64,bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } },
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{ "mov", 2, 0x88, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
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/* In the 64bit mode the short form mov immediate is redefined to have
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64bit displacement value. */
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@ -109,7 +109,7 @@ static const template i386_optab[] =
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{ "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} },
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{ "mov", 2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} },
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{ "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} },
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{ "mov", 2, 0x0f24, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} },
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{ "mov", 2, 0x0f24, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} },
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{ "movabs",2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } },
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{ "movabs",2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } },
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@ -219,8 +219,8 @@ static const template i386_optab[] =
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{"cli", 0, 0xfa, X, 0, NoSuf, { 0, 0, 0} },
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{"clts", 0, 0x0f06, X, Cpu286, NoSuf, { 0, 0, 0} },
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{"cmc", 0, 0xf5, X, 0, NoSuf, { 0, 0, 0} },
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{"lahf", 0, 0x9f, X, CpuNo64,NoSuf, { 0, 0, 0} },
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{"sahf", 0, 0x9e, X, CpuNo64,NoSuf, { 0, 0, 0} },
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{"lahf", 0, 0x9f, X, 0, NoSuf, { 0, 0, 0} },
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{"sahf", 0, 0x9e, X, 0, NoSuf, { 0, 0, 0} },
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{"pushf", 0, 0x9c, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} },
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{"pushf", 0, 0x9c, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
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{"popf", 0, 0x9d, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} },
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@ -578,7 +578,7 @@ static const template i386_optab[] =
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{"sgdt", 1, 0x0f01, 0, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} },
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{"sgdt", 1, 0x0f01, 0, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} },
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{"sidt", 1, 0x0f01, 1, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} },
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{"sidt", 1, 0x0f01, 1, Cpu64, q_Suf|Modrm, { LLongMem, 0, 0} },
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{"sidt", 1, 0x0f01, 1, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} },
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{"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} },
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{"sldt", 1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
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{"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} },
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@ -912,8 +912,8 @@ static const template i386_optab[] =
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/* Pentium II/Pentium Pro extensions. */
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{"sysenter",0, 0x0f34, X, Cpu686, NoSuf, { 0, 0, 0} },
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{"sysexit", 0, 0x0f35, X, Cpu686, NoSuf, { 0, 0, 0} },
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{"fxsave", 1, 0x0fae, 0, Cpu686, FP|Modrm, { LLongMem, 0, 0} },
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{"fxrstor", 1, 0x0fae, 1, Cpu686, FP|Modrm, { LLongMem, 0, 0} },
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{"fxsave", 1, 0x0fae, 0, Cpu686, q_Suf|Modrm, { LLongMem, 0, 0} },
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{"fxrstor", 1, 0x0fae, 1, Cpu686, q_Suf|Modrm, { LLongMem, 0, 0} },
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{"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} },
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/* official undefined instr. */
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{"ud2", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} },
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@ -1316,6 +1316,7 @@ static const template i386_optab[] =
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{"addsubpd", 2, 0x660fd0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"addsubps", 2, 0xf20fd0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"cmpxchg16b",1, 0x0fc7, 1, CpuPNI|Cpu64, NoSuf|Modrm|Rex64, { LLongMem, 0, 0} },
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{"fisttp", 1, 0xdf, 1, CpuPNI, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} },
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{"fisttp", 1, 0xdd, 1, CpuPNI, q_FP|Modrm, { LLongMem, 0, 0} },
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{"fisttpll", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} },
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