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2012-10-04 Chao-ying Fu <fu@mips.com>

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Steve Ellcey  <sellcey@mips.com>

	* mips/mips3264r2.igen (rdhwr): New.
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Steve Ellcey
2012-10-03 21:11:46 +00:00
parent cbf1fdc93b
commit 37cb8f8e70
2 changed files with 16 additions and 0 deletions
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5
sim/mips/ChangeLog
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@ -1,3 +1,8 @@
2012-10-04 Chao-ying Fu <fu@mips.com>
Steve Ellcey <sellcey@mips.com>
* mips/mips3264r2.igen (rdhwr): New.
2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com> 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
* configure.ac: Always link against dv-sockser.o. * configure.ac: Always link against dv-sockser.o.

11
sim/mips/mips3264r2.igen
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@ -241,6 +241,17 @@
} }
011111,00000,5.RT,5.RD,00000,111011::32::RDHWR
"rdhwr r<RT>, r<RD>"
*mips32r2:
*mips64r2:
{
// Return 0 for all hardware registers currently
GPR[RT] = EXTEND32 (0);
TRACE_ALU_RESULT1 (GPR[RT]);
}
011111,00000,5.RT,5.RD,00010,100000::32::WSBH 011111,00000,5.RT,5.RD,00010,100000::32::WSBH
"wsbh r<RD>, r<RT>" "wsbh r<RD>, r<RT>"
*mips32r2: *mips32r2: