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* config/bfin-parse.y (asm_1): Fix reduce/reduce conflicts.

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Jie Zhang
2008-09-26 04:49:17 +00:00
parent 181b26eaf1
commit 37b3293520
2 changed files with 14 additions and 12 deletions
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4
gas/ChangeLog
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@ -1,3 +1,7 @@
2008-09-26 Jie Zhang <jie.zhang@analog.com>
* config/bfin-parse.y (asm_1): Fix reduce/reduce conflicts.
2008-09-24 Richard Henderson <rth@redhat.com> 2008-09-24 Richard Henderson <rth@redhat.com>
* dw2gencfi.c (DWARF2_ADDR_SIZE): Provide default. * dw2gencfi.c (DWARF2_ADDR_SIZE): Provide default.

22
gas/config/bfin-parse.y
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@ -1932,22 +1932,20 @@ asm_1:
else else
return yyerror ("Bad shift value or register"); return yyerror ("Bad shift value or register");
} }
| HALF_REG ASSIGN HALF_REG LESS_LESS expr
{
if (IS_UIMM ($5, 4))
{
notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
$$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
}
else
return yyerror ("Bad shift value");
}
| HALF_REG ASSIGN HALF_REG LESS_LESS expr smod | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
{ {
if (IS_UIMM ($5, 4)) if (IS_UIMM ($5, 4))
{ {
notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n"); if ($6.s0)
$$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3)); {
notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n");
$$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
}
else
{
notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
$$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
}
} }
else else
return yyerror ("Bad shift value"); return yyerror ("Bad shift value");