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x86: convert RegSIMD and RegMMX from bitfield to enumerator

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This is to further shrink the operand type representation.
This commit is contained in:
Jan Beulich
2019-11-08 09:05:36 +01:00
parent 4a5c67ed84
commit 3528c362d9
9 changed files with 19240 additions and 19217 deletions
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8
gas/ChangeLog
View File

@ -1,3 +1,11 @@
2019-11-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_mem_size, operand_size_match,
operand_type_register_match, pi, check_VecOperands, match_template,
check_byte_reg, check_long_reg, check_qword_reg, process_operands,
build_modrm_byte, parse_real_register): Use "class" instead of
"regsimd" / "regmmx" fields.
2019-11-08 Jan Beulich <jbeulich@suse.com> 2019-11-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (pi, check_byte_reg, build_modrm_byte, * config/tc-i386.c (pi, check_byte_reg, build_modrm_byte,

88
gas/config/tc-i386.c
View File

@ -2030,7 +2030,7 @@ match_mem_size (const insn_template *t, unsigned int wanted,
operands at the same time, some special casing is needed operands at the same time, some special casing is needed
here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
down-conversion vpmov*. */ down-conversion vpmov*. */
|| ((t->operand_types[wanted].bitfield.regsimd || ((t->operand_types[wanted].bitfield.class == RegSIMD
&& !t->opcode_modifier.broadcast && !t->opcode_modifier.broadcast
&& (t->operand_types[wanted].bitfield.byte && (t->operand_types[wanted].bitfield.byte
|| t->operand_types[wanted].bitfield.word || t->operand_types[wanted].bitfield.word
@ -2065,7 +2065,8 @@ operand_size_match (const insn_template *t)
/* Check memory and accumulator operand size. */ /* Check memory and accumulator operand size. */
for (j = 0; j < i.operands; j++) for (j = 0; j < i.operands; j++)
{ {
if (i.types[j].bitfield.class != Reg && !i.types[j].bitfield.regsimd if (i.types[j].bitfield.class != Reg
&& i.types[j].bitfield.class != RegSIMD
&& t->operand_types[j].bitfield.anysize) && t->operand_types[j].bitfield.anysize)
continue; continue;
@ -2076,7 +2077,7 @@ operand_size_match (const insn_template *t)
break; break;
} }
if (t->operand_types[j].bitfield.regsimd if (t->operand_types[j].bitfield.class == RegSIMD
&& !match_simd_size (t, j, j)) && !match_simd_size (t, j, j))
{ {
match = 0; match = 0;
@ -2116,7 +2117,7 @@ mismatch:
&& !match_operand_size (t, j, given)) && !match_operand_size (t, j, given))
goto mismatch; goto mismatch;
if (t->operand_types[j].bitfield.regsimd if (t->operand_types[j].bitfield.class == RegSIMD
&& !match_simd_size (t, j, given)) && !match_simd_size (t, j, given))
goto mismatch; goto mismatch;
@ -2173,17 +2174,17 @@ operand_type_register_match (i386_operand_type g0,
i386_operand_type t1) i386_operand_type t1)
{ {
if (g0.bitfield.class != Reg if (g0.bitfield.class != Reg
&& !g0.bitfield.regsimd && g0.bitfield.class != RegSIMD
&& (!operand_type_check (g0, anymem) && (!operand_type_check (g0, anymem)
|| g0.bitfield.unspecified || g0.bitfield.unspecified
|| !t0.bitfield.regsimd)) || t0.bitfield.class != RegSIMD))
return 1; return 1;
if (g1.bitfield.class != Reg if (g1.bitfield.class != Reg
&& !g1.bitfield.regsimd && g1.bitfield.class != RegSIMD
&& (!operand_type_check (g1, anymem) && (!operand_type_check (g1, anymem)
|| g1.bitfield.unspecified || g1.bitfield.unspecified
|| !t1.bitfield.regsimd)) || t1.bitfield.class != RegSIMD))
return 1; return 1;
if (g0.bitfield.byte == g1.bitfield.byte if (g0.bitfield.byte == g1.bitfield.byte
@ -3046,8 +3047,8 @@ pi (const char *line, i386_insn *x)
pt (x->types[j]); pt (x->types[j]);
fprintf (stdout, "\n"); fprintf (stdout, "\n");
if (x->types[j].bitfield.class == Reg if (x->types[j].bitfield.class == Reg
|| x->types[j].bitfield.regmmx || x->types[j].bitfield.class == RegMMX
|| x->types[j].bitfield.regsimd || x->types[j].bitfield.class == RegSIMD
|| x->types[j].bitfield.class == SReg || x->types[j].bitfield.class == SReg
|| x->types[j].bitfield.class == RegCR || x->types[j].bitfield.class == RegCR
|| x->types[j].bitfield.class == RegDR || x->types[j].bitfield.class == RegDR
@ -5380,10 +5381,10 @@ check_VecOperands (const insn_template *t)
gas_assert (i.reg_operands == 2 || i.mask); gas_assert (i.reg_operands == 2 || i.mask);
if (i.reg_operands == 2 && !i.mask) if (i.reg_operands == 2 && !i.mask)
{ {
gas_assert (i.types[0].bitfield.regsimd); gas_assert (i.types[0].bitfield.class == RegSIMD);
gas_assert (i.types[0].bitfield.xmmword gas_assert (i.types[0].bitfield.xmmword
|| i.types[0].bitfield.ymmword); || i.types[0].bitfield.ymmword);
gas_assert (i.types[2].bitfield.regsimd); gas_assert (i.types[2].bitfield.class == RegSIMD);
gas_assert (i.types[2].bitfield.xmmword gas_assert (i.types[2].bitfield.xmmword
|| i.types[2].bitfield.ymmword); || i.types[2].bitfield.ymmword);
if (operand_check == check_none) if (operand_check == check_none)
@ -5404,7 +5405,7 @@ check_VecOperands (const insn_template *t)
} }
else if (i.reg_operands == 1 && i.mask) else if (i.reg_operands == 1 && i.mask)
{ {
if (i.types[1].bitfield.regsimd if (i.types[1].bitfield.class == RegSIMD
&& (i.types[1].bitfield.xmmword && (i.types[1].bitfield.xmmword
|| i.types[1].bitfield.ymmword || i.types[1].bitfield.ymmword
|| i.types[1].bitfield.zmmword) || i.types[1].bitfield.zmmword)
@ -5595,7 +5596,7 @@ check_VecOperands (const insn_template *t)
else if (!i.types[op].bitfield.unspecified) else if (!i.types[op].bitfield.unspecified)
type = &i.types[op]; type = &i.types[op];
} }
else if (i.types[op].bitfield.regsimd else if (i.types[op].bitfield.class == RegSIMD
&& t->opcode_modifier.evex != EVEXLIG) && t->opcode_modifier.evex != EVEXLIG)
{ {
if (i.types[op].bitfield.zmmword) if (i.types[op].bitfield.zmmword)
@ -5801,10 +5802,10 @@ match_template (char mnem_suffix)
&& !t->opcode_modifier.broadcast && !t->opcode_modifier.broadcast
&& !intel_float_operand (t->name)) && !intel_float_operand (t->name))
: intel_float_operand (t->name) != 2) : intel_float_operand (t->name) != 2)
&& ((!operand_types[0].bitfield.regmmx && ((operand_types[0].bitfield.class != RegMMX
&& !operand_types[0].bitfield.regsimd) && operand_types[0].bitfield.class != RegSIMD)
|| (!operand_types[t->operands > 1].bitfield.regmmx || (operand_types[t->operands > 1].bitfield.class != RegMMX
&& !operand_types[t->operands > 1].bitfield.regsimd)) && operand_types[t->operands > 1].bitfield.class != RegSIMD))
&& (t->base_opcode != 0x0fc7 && (t->base_opcode != 0x0fc7
|| t->extension_opcode != 1 /* cmpxchg8b */)) || t->extension_opcode != 1 /* cmpxchg8b */))
continue; continue;
@ -5816,10 +5817,11 @@ match_template (char mnem_suffix)
? (!t->opcode_modifier.ignoresize ? (!t->opcode_modifier.ignoresize
&& !intel_float_operand (t->name)) && !intel_float_operand (t->name))
: intel_float_operand (t->name) != 2) : intel_float_operand (t->name) != 2)
&& ((!operand_types[0].bitfield.regmmx && ((operand_types[0].bitfield.class != RegMMX
&& !operand_types[0].bitfield.regsimd) && operand_types[0].bitfield.class != RegSIMD)
|| (!operand_types[t->operands > 1].bitfield.regmmx || (operand_types[t->operands > 1].bitfield.class != RegMMX
&& !operand_types[t->operands > 1].bitfield.regsimd))) && operand_types[t->operands > 1].bitfield.class
!= RegSIMD)))
continue; continue;
/* Do not verify operands when there are none. */ /* Do not verify operands when there are none. */
@ -5995,8 +5997,8 @@ check_reverse:
found_reverse_match = Opcode_FloatD; found_reverse_match = Opcode_FloatD;
else if (operand_types[0].bitfield.xmmword else if (operand_types[0].bitfield.xmmword
|| operand_types[i.operands - 1].bitfield.xmmword || operand_types[i.operands - 1].bitfield.xmmword
|| operand_types[0].bitfield.regmmx || operand_types[0].bitfield.class == RegMMX
|| operand_types[i.operands - 1].bitfield.regmmx || operand_types[i.operands - 1].bitfield.class == RegMMX
|| is_any_vex_encoding(t)) || is_any_vex_encoding(t))
found_reverse_match = (t->base_opcode & 0xee) != 0x6e found_reverse_match = (t->base_opcode & 0xee) != 0x6e
? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
@ -6602,8 +6604,8 @@ check_byte_reg (void)
} }
/* Any other register is bad. */ /* Any other register is bad. */
if (i.types[op].bitfield.class == Reg if (i.types[op].bitfield.class == Reg
|| i.types[op].bitfield.regmmx || i.types[op].bitfield.class == RegMMX
|| i.types[op].bitfield.regsimd || i.types[op].bitfield.class == RegSIMD
|| i.types[op].bitfield.class == SReg || i.types[op].bitfield.class == SReg
|| i.types[op].bitfield.class == RegCR || i.types[op].bitfield.class == RegCR
|| i.types[op].bitfield.class == RegDR || i.types[op].bitfield.class == RegDR
@ -6675,7 +6677,7 @@ check_long_reg (void)
{ {
if (intel_syntax if (intel_syntax
&& i.tm.opcode_modifier.toqword && i.tm.opcode_modifier.toqword
&& !i.types[0].bitfield.regsimd) && i.types[0].bitfield.class != RegSIMD)
{ {
/* Convert to QWORD. We want REX byte. */ /* Convert to QWORD. We want REX byte. */
i.suffix = QWORD_MNEM_SUFFIX; i.suffix = QWORD_MNEM_SUFFIX;
@ -6726,7 +6728,7 @@ check_qword_reg (void)
lowering is more complicated. */ lowering is more complicated. */
if (intel_syntax if (intel_syntax
&& i.tm.opcode_modifier.todword && i.tm.opcode_modifier.todword
&& !i.types[0].bitfield.regsimd) && i.types[0].bitfield.class != RegSIMD)
{ {
/* Convert to DWORD. We don't want REX byte. */ /* Convert to DWORD. We don't want REX byte. */
i.suffix = LONG_MNEM_SUFFIX; i.suffix = LONG_MNEM_SUFFIX;
@ -6903,7 +6905,7 @@ process_operands (void)
/* Keep xmm0 for instructions with VEX prefix and 3 /* Keep xmm0 for instructions with VEX prefix and 3
sources. */ sources. */
i.tm.operand_types[0].bitfield.acc = 0; i.tm.operand_types[0].bitfield.acc = 0;
i.tm.operand_types[0].bitfield.regsimd = 1; i.tm.operand_types[0].bitfield.class = RegSIMD;
goto duplicate; goto duplicate;
} }
else else
@ -6993,7 +6995,7 @@ duplicate:
unsigned int regnum, first_reg_in_group, last_reg_in_group; unsigned int regnum, first_reg_in_group, last_reg_in_group;
/* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd); gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD);
regnum = register_number (i.op[1].regs); regnum = register_number (i.op[1].regs);
first_reg_in_group = regnum & ~3; first_reg_in_group = regnum & ~3;
last_reg_in_group = first_reg_in_group + 3; last_reg_in_group = first_reg_in_group + 3;
@ -7138,7 +7140,7 @@ build_modrm_byte (void)
|| (i.reg_operands == 3 && i.mem_operands == 1)) || (i.reg_operands == 3 && i.mem_operands == 1))
&& i.tm.opcode_modifier.vexvvvv == VEXXDS && i.tm.opcode_modifier.vexvvvv == VEXXDS
&& i.tm.opcode_modifier.vexw && i.tm.opcode_modifier.vexw
&& i.tm.operand_types[dest].bitfield.regsimd); && i.tm.operand_types[dest].bitfield.class == RegSIMD);
/* If VexW1 is set, the first non-immediate operand is the source and /* If VexW1 is set, the first non-immediate operand is the source and
the second non-immediate one is encoded in the immediate operand. */ the second non-immediate one is encoded in the immediate operand. */
@ -7162,7 +7164,7 @@ build_modrm_byte (void)
i.types[i.operands] = imm8; i.types[i.operands] = imm8;
i.operands++; i.operands++;
gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD);
exp->X_op = O_constant; exp->X_op = O_constant;
exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
@ -7176,13 +7178,13 @@ build_modrm_byte (void)
/* Turn on Imm8 again so that output_imm will generate it. */ /* Turn on Imm8 again so that output_imm will generate it. */
i.types[0].bitfield.imm8 = 1; i.types[0].bitfield.imm8 = 1;
gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD);
i.op[0].imms->X_add_number i.op[0].imms->X_add_number
|= register_number (i.op[reg_slot].regs) << 4; |= register_number (i.op[reg_slot].regs) << 4;
gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
} }
gas_assert (i.tm.operand_types[nds].bitfield.regsimd); gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD);
i.vex.register_specifier = i.op[nds].regs; i.vex.register_specifier = i.op[nds].regs;
} }
else else
@ -7304,7 +7306,7 @@ build_modrm_byte (void)
if ((dest + 1) >= i.operands if ((dest + 1) >= i.operands
|| ((op.bitfield.class != Reg || ((op.bitfield.class != Reg
|| (!op.bitfield.dword && !op.bitfield.qword)) || (!op.bitfield.dword && !op.bitfield.qword))
&& !op.bitfield.regsimd && op.bitfield.class != RegSIMD
&& !operand_type_equal (&op, &regmask))) && !operand_type_equal (&op, &regmask)))
abort (); abort ();
i.vex.register_specifier = i.op[vvvv].regs; i.vex.register_specifier = i.op[vvvv].regs;
@ -7324,11 +7326,11 @@ build_modrm_byte (void)
{ {
i.rm.reg = i.op[dest].regs->reg_num; i.rm.reg = i.op[dest].regs->reg_num;
i.rm.regmem = i.op[source].regs->reg_num; i.rm.regmem = i.op[source].regs->reg_num;
if (i.op[dest].regs->reg_type.bitfield.regmmx if (i.op[dest].regs->reg_type.bitfield.class == RegMMX
|| i.op[source].regs->reg_type.bitfield.regmmx) || i.op[source].regs->reg_type.bitfield.class == RegMMX)
i.has_regmmx = TRUE; i.has_regmmx = TRUE;
else if (i.op[dest].regs->reg_type.bitfield.regsimd else if (i.op[dest].regs->reg_type.bitfield.class == RegSIMD
|| i.op[source].regs->reg_type.bitfield.regsimd) || i.op[source].regs->reg_type.bitfield.class == RegSIMD)
{ {
if (i.types[dest].bitfield.zmmword if (i.types[dest].bitfield.zmmword
|| i.types[source].bitfield.zmmword) || i.types[source].bitfield.zmmword)
@ -7687,7 +7689,7 @@ build_modrm_byte (void)
|| i.types[op].bitfield.class == RegDR || i.types[op].bitfield.class == RegDR
|| i.types[op].bitfield.class == RegTR) || i.types[op].bitfield.class == RegTR)
break; break;
if (i.types[op].bitfield.regsimd) if (i.types[op].bitfield.class == RegSIMD)
{ {
if (i.types[op].bitfield.zmmword) if (i.types[op].bitfield.zmmword)
i.has_regzmm = TRUE; i.has_regzmm = TRUE;
@ -7697,7 +7699,7 @@ build_modrm_byte (void)
i.has_regxmm = TRUE; i.has_regxmm = TRUE;
break; break;
} }
if (i.types[op].bitfield.regmmx) if (i.types[op].bitfield.class == RegMMX)
{ {
i.has_regmmx = TRUE; i.has_regmmx = TRUE;
break; break;
@ -7763,7 +7765,7 @@ build_modrm_byte (void)
if ((type->bitfield.class != Reg if ((type->bitfield.class != Reg
|| (!type->bitfield.dword && !type->bitfield.qword)) || (!type->bitfield.dword && !type->bitfield.qword))
&& !type->bitfield.regsimd && type->bitfield.class != RegSIMD
&& !operand_type_equal (type, &regmask)) && !operand_type_equal (type, &regmask))
abort (); abort ();
@ -10928,7 +10930,7 @@ parse_real_register (char *reg_string, char **end_op)
&& !cpu_arch_flags.bitfield.cpui386) && !cpu_arch_flags.bitfield.cpui386)
return (const reg_entry *) NULL; return (const reg_entry *) NULL;
if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx) if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx)
return (const reg_entry *) NULL; return (const reg_entry *) NULL;
if (!cpu_arch_flags.bitfield.cpuavx512f) if (!cpu_arch_flags.bitfield.cpuavx512f)

16
opcodes/ChangeLog
View File

@ -1,3 +1,19 @@
2019-11-08 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init): Add Class= to
OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
OPERAND_TYPE_REGZMM entries.
(operand_classes): Add RegMMX and RegSIMD entries.
(operand_types): Drop RegMMX and RegSIMD entries.
* i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
(RegMMX, RegSIMD): Delete.
(union i386_operand_type): Remove regmmx and regsimd fields.
* i386-opc.tbl (RegMMX): Define.
(RegXMM, RegYMM, RegZMM): Add Class=.
* i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
Class=RegSIMD.
* i386-init.h, i386-tbl.h: Re-generate.
2019-11-08 Jan Beulich <jbeulich@suse.com> 2019-11-08 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init): Add Class= to * i386-gen.c (operand_type_init): Add Class= to

12
opcodes/i386-gen.c
View File

@ -440,13 +440,13 @@ static initializer operand_type_init[] =
{ "OPERAND_TYPE_JUMPABSOLUTE", { "OPERAND_TYPE_JUMPABSOLUTE",
"JumpAbsolute" }, "JumpAbsolute" },
{ "OPERAND_TYPE_REGMMX", { "OPERAND_TYPE_REGMMX",
"RegMMX" }, "Class=RegMMX" },
{ "OPERAND_TYPE_REGXMM", { "OPERAND_TYPE_REGXMM",
"RegSIMD|Xmmword" }, "Class=RegSIMD|Xmmword" },
{ "OPERAND_TYPE_REGYMM", { "OPERAND_TYPE_REGYMM",
"RegSIMD|Ymmword" }, "Class=RegSIMD|Ymmword" },
{ "OPERAND_TYPE_REGZMM", { "OPERAND_TYPE_REGZMM",
"RegSIMD|Zmmword" }, "Class=RegSIMD|Zmmword" },
{ "OPERAND_TYPE_REGMASK", { "OPERAND_TYPE_REGMASK",
"RegMask" }, "RegMask" },
{ "OPERAND_TYPE_ESSEG", { "OPERAND_TYPE_ESSEG",
@ -687,14 +687,14 @@ static const struct {
CLASS (RegCR), CLASS (RegCR),
CLASS (RegDR), CLASS (RegDR),
CLASS (RegTR), CLASS (RegTR),
CLASS (RegMMX),
CLASS (RegSIMD),
}; };
#undef CLASS #undef CLASS
static bitfield operand_types[] = static bitfield operand_types[] =
{ {
BITFIELD (RegMMX),
BITFIELD (RegSIMD),
BITFIELD (RegMask), BITFIELD (RegMask),
BITFIELD (Imm1), BITFIELD (Imm1),
BITFIELD (Imm8), BITFIELD (Imm8),

174
opcodes/i386-init.h
View File

@ -1365,196 +1365,196 @@
#define OPERAND_TYPE_NONE \ #define OPERAND_TYPE_NONE \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REG8 \ #define OPERAND_TYPE_REG8 \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REG16 \ #define OPERAND_TYPE_REG16 \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REG32 \ #define OPERAND_TYPE_REG32 \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REG64 \ #define OPERAND_TYPE_REG64 \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM1 \ #define OPERAND_TYPE_IMM1 \
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM8 \ #define OPERAND_TYPE_IMM8 \
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM8S \ #define OPERAND_TYPE_IMM8S \
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM16 \ #define OPERAND_TYPE_IMM16 \
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32 \ #define OPERAND_TYPE_IMM32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32S \ #define OPERAND_TYPE_IMM32S \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM64 \ #define OPERAND_TYPE_IMM64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_BASEINDEX \ #define OPERAND_TYPE_BASEINDEX \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DISP8 \ #define OPERAND_TYPE_DISP8 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DISP16 \ #define OPERAND_TYPE_DISP16 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DISP32 \ #define OPERAND_TYPE_DISP32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DISP32S \ #define OPERAND_TYPE_DISP32S \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DISP64 \ #define OPERAND_TYPE_DISP64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_INOUTPORTREG \ #define OPERAND_TYPE_INOUTPORTREG \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_SHIFTCOUNT \ #define OPERAND_TYPE_SHIFTCOUNT \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_CONTROL \ #define OPERAND_TYPE_CONTROL \
{ { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_TEST \ #define OPERAND_TYPE_TEST \
{ { 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DEBUG \ #define OPERAND_TYPE_DEBUG \
{ { 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_FLOATREG \ #define OPERAND_TYPE_FLOATREG \
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_FLOATACC \ #define OPERAND_TYPE_FLOATACC \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_SREG \ #define OPERAND_TYPE_SREG \
{ { 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_JUMPABSOLUTE \ #define OPERAND_TYPE_JUMPABSOLUTE \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REGMMX \ #define OPERAND_TYPE_REGMMX \
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REGXMM \ #define OPERAND_TYPE_REGXMM \
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REGYMM \ #define OPERAND_TYPE_REGYMM \
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REGZMM \ #define OPERAND_TYPE_REGZMM \
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REGMASK \ #define OPERAND_TYPE_REGMASK \
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_ESSEG \ #define OPERAND_TYPE_ESSEG \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_ACC8 \ #define OPERAND_TYPE_ACC8 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_ACC16 \ #define OPERAND_TYPE_ACC16 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_ACC32 \ #define OPERAND_TYPE_ACC32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_ACC64 \ #define OPERAND_TYPE_ACC64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_DISP16_32 \ #define OPERAND_TYPE_DISP16_32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_ANYDISP \ #define OPERAND_TYPE_ANYDISP \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM16_32 \ #define OPERAND_TYPE_IMM16_32 \
{ { 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM16_32S \ #define OPERAND_TYPE_IMM16_32S \
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM16_32_32S \ #define OPERAND_TYPE_IMM16_32_32S \
{ { 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32_64 \ #define OPERAND_TYPE_IMM32_64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32_32S_DISP32 \ #define OPERAND_TYPE_IMM32_32S_DISP32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM64_DISP64 \ #define OPERAND_TYPE_IMM64_DISP64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32_32S_64_DISP32 \ #define OPERAND_TYPE_IMM32_32S_64_DISP32 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_IMM32_32S_64_DISP32_64 \ #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_ANYIMM \ #define OPERAND_TYPE_ANYIMM \
{ { 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define OPERAND_TYPE_REGBND \ #define OPERAND_TYPE_REGBND \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } } 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }

8
opcodes/i386-opc.h
View File

@ -713,6 +713,8 @@ enum operand_class
RegCR, /* Control register */ RegCR, /* Control register */
RegDR, /* Debug register */ RegDR, /* Debug register */
RegTR, /* Test register */ RegTR, /* Test register */
RegMMX, /* MMX register */
RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
}; };
/* Position of operand_type bits. */ /* Position of operand_type bits. */
@ -721,10 +723,6 @@ enum
{ {
/* Class */ /* Class */
Class = CLASS_WIDTH - 1, Class = CLASS_WIDTH - 1,
/* MMX register */
RegMMX,
/* Vector registers */
RegSIMD,
/* Vector Mask registers */ /* Vector Mask registers */
RegMask, RegMask,
/* 1 bit immediate */ /* 1 bit immediate */
@ -814,8 +812,6 @@ typedef union i386_operand_type
struct struct
{ {
unsigned int class:CLASS_WIDTH; unsigned int class:CLASS_WIDTH;
unsigned int regmmx:1;
unsigned int regsimd:1;
unsigned int regmask:1; unsigned int regmask:1;
unsigned int imm1:1; unsigned int imm1:1;
unsigned int imm8:1; unsigned int imm8:1;

7
opcodes/i386-opc.tbl
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@ -36,9 +36,10 @@
#define Debug Class=RegDR #define Debug Class=RegDR
#define Test Class=RegTR #define Test Class=RegTR
#define RegXMM RegSIMD|Xmmword #define RegMMX Class=RegMMX
#define RegYMM RegSIMD|Ymmword #define RegXMM Class=RegSIMD|Xmmword
#define RegZMM RegSIMD|Zmmword #define RegYMM Class=RegSIMD|Ymmword
#define RegZMM Class=RegSIMD|Zmmword
#define Size16 Size=SIZE16 #define Size16 Size=SIZE16
#define Size32 Size=SIZE32 #define Size32 Size=SIZE32

208
opcodes/i386-reg.tbl
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@ -172,112 +172,112 @@ tr5, Class=RegTR, 0, 5, Dw2Inval, Dw2Inval
tr6, Class=RegTR, 0, 6, Dw2Inval, Dw2Inval tr6, Class=RegTR, 0, 6, Dw2Inval, Dw2Inval
tr7, Class=RegTR, 0, 7, Dw2Inval, Dw2Inval tr7, Class=RegTR, 0, 7, Dw2Inval, Dw2Inval
// MMX and simd registers. // MMX and simd registers.
mm0, RegMMX, 0, 0, 29, 41 mm0, Class=RegMMX, 0, 0, 29, 41
mm1, RegMMX, 0, 1, 30, 42 mm1, Class=RegMMX, 0, 1, 30, 42
mm2, RegMMX, 0, 2, 31, 43 mm2, Class=RegMMX, 0, 2, 31, 43
mm3, RegMMX, 0, 3, 32, 44 mm3, Class=RegMMX, 0, 3, 32, 44
mm4, RegMMX, 0, 4, 33, 45 mm4, Class=RegMMX, 0, 4, 33, 45
mm5, RegMMX, 0, 5, 34, 46 mm5, Class=RegMMX, 0, 5, 34, 46
mm6, RegMMX, 0, 6, 35, 47 mm6, Class=RegMMX, 0, 6, 35, 47
mm7, RegMMX, 0, 7, 36, 48 mm7, Class=RegMMX, 0, 7, 36, 48
xmm0, RegSIMD|Acc|Xmmword, 0, 0, 21, 17 xmm0, Class=RegSIMD|Acc|Xmmword, 0, 0, 21, 17
xmm1, RegSIMD|Xmmword, 0, 1, 22, 18 xmm1, Class=RegSIMD|Xmmword, 0, 1, 22, 18
xmm2, RegSIMD|Xmmword, 0, 2, 23, 19 xmm2, Class=RegSIMD|Xmmword, 0, 2, 23, 19
xmm3, RegSIMD|Xmmword, 0, 3, 24, 20 xmm3, Class=RegSIMD|Xmmword, 0, 3, 24, 20
xmm4, RegSIMD|Xmmword, 0, 4, 25, 21 xmm4, Class=RegSIMD|Xmmword, 0, 4, 25, 21
xmm5, RegSIMD|Xmmword, 0, 5, 26, 22 xmm5, Class=RegSIMD|Xmmword, 0, 5, 26, 22
xmm6, RegSIMD|Xmmword, 0, 6, 27, 23 xmm6, Class=RegSIMD|Xmmword, 0, 6, 27, 23
xmm7, RegSIMD|Xmmword, 0, 7, 28, 24 xmm7, Class=RegSIMD|Xmmword, 0, 7, 28, 24
xmm8, RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25 xmm8, Class=RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25
xmm9, RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26 xmm9, Class=RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26
xmm10, RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27 xmm10, Class=RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27
xmm11, RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28 xmm11, Class=RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28
xmm12, RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29 xmm12, Class=RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29
xmm13, RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30 xmm13, Class=RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30
xmm14, RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31 xmm14, Class=RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31
xmm15, RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32 xmm15, Class=RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32
xmm16, RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67 xmm16, Class=RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67
xmm17, RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68 xmm17, Class=RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68
xmm18, RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69 xmm18, Class=RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69
xmm19, RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70 xmm19, Class=RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70
xmm20, RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71 xmm20, Class=RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71
xmm21, RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72 xmm21, Class=RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72
xmm22, RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73 xmm22, Class=RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73
xmm23, RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74 xmm23, Class=RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74
xmm24, RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75 xmm24, Class=RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75
xmm25, RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76 xmm25, Class=RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76
xmm26, RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77 xmm26, Class=RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77
xmm27, RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78 xmm27, Class=RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78
xmm28, RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79 xmm28, Class=RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79
xmm29, RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80 xmm29, Class=RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80
xmm30, RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81 xmm30, Class=RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81
xmm31, RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82 xmm31, Class=RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82
// AVX registers. // AVX registers.
ymm0, RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval ymm0, Class=RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval
ymm1, RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval ymm1, Class=RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval
ymm2, RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval ymm2, Class=RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval
ymm3, RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval ymm3, Class=RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval
ymm4, RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval ymm4, Class=RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval
ymm5, RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval ymm5, Class=RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval
ymm6, RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval ymm6, Class=RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval
ymm7, RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval ymm7, Class=RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval
ymm8, RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval ymm8, Class=RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval
ymm9, RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval ymm9, Class=RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval
ymm10, RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval ymm10, Class=RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval
ymm11, RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval ymm11, Class=RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval
ymm12, RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval ymm12, Class=RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval
ymm13, RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval ymm13, Class=RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval
ymm14, RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval ymm14, Class=RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval
ymm15, RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval ymm15, Class=RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval
ymm16, RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval ymm16, Class=RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval
ymm17, RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval ymm17, Class=RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval
ymm18, RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval ymm18, Class=RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval
ymm19, RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval ymm19, Class=RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval
ymm20, RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval ymm20, Class=RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval
ymm21, RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval ymm21, Class=RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval
ymm22, RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval ymm22, Class=RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval
ymm23, RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval ymm23, Class=RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval
ymm24, RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval ymm24, Class=RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
ymm25, RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval ymm25, Class=RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
ymm26, RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval ymm26, Class=RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
ymm27, RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval ymm27, Class=RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
ymm28, RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval ymm28, Class=RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
ymm29, RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval ymm29, Class=RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
ymm30, RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval ymm30, Class=RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
ymm31, RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval ymm31, Class=RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
// AVX512 registers. // AVX512 registers.
zmm0, RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval zmm0, Class=RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval
zmm1, RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval zmm1, Class=RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval
zmm2, RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval zmm2, Class=RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval
zmm3, RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval zmm3, Class=RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval
zmm4, RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval zmm4, Class=RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval
zmm5, RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval zmm5, Class=RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval
zmm6, RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval zmm6, Class=RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval
zmm7, RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval zmm7, Class=RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval
zmm8, RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval zmm8, Class=RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval
zmm9, RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval zmm9, Class=RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval
zmm10, RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval zmm10, Class=RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval
zmm11, RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval zmm11, Class=RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval
zmm12, RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval zmm12, Class=RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval
zmm13, RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval zmm13, Class=RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval
zmm14, RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval zmm14, Class=RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval
zmm15, RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval zmm15, Class=RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval
zmm16, RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval zmm16, Class=RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval
zmm17, RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval zmm17, Class=RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval
zmm18, RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval zmm18, Class=RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval
zmm19, RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval zmm19, Class=RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval
zmm20, RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval zmm20, Class=RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval
zmm21, RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval zmm21, Class=RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval
zmm22, RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval zmm22, Class=RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval
zmm23, RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval zmm23, Class=RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval
zmm24, RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval zmm24, Class=RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
zmm25, RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval zmm25, Class=RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
zmm26, RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval zmm26, Class=RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
zmm27, RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval zmm27, Class=RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
zmm28, RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
zmm29, RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
zmm30, RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
zmm31, RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
// Bound registers for MPX // Bound registers for MPX
bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval
bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval

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opcodes/i386-tbl.h
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