espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-22 11:00:01 +08:00
Code Issues Packages Projects Releases Wiki Activity

ppc/svp64: support LibreSOC architecture

Browse Source 
This patch adds support for LibreSOC machine and SVP64 extension flag
for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm
Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit
Prefixed instruction format implementing SV. Funded by NLnet through EU
Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly
submitted via the OpenPOWER Foundation ISA Working Group via the
newly-created External RFC Process.

For more details, visit https://libre-soc.org.
This commit is contained in:
Dmitry Selyutin
2022-07-25 16:10:14 +03:00
committed by Alan Modra
parent df4860daad
commit 33ae8a3ae3
4 changed files with 19 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
gas/config/tc-ppc.c
View File

@ -1382,6 +1382,8 @@ PowerPC options:\n"));
fprintf (stream, _("\ fprintf (stream, _("\
-mpower10, -mpwr10 generate code for Power10 architecture\n")); -mpower10, -mpwr10 generate code for Power10 architecture\n"));
fprintf (stream, _("\ fprintf (stream, _("\
-mlibresoc generate code for Libre-SOC architecture\n"));
fprintf (stream, _("\
-mcell generate code for Cell Broadband Engine architecture\n")); -mcell generate code for Cell Broadband Engine architecture\n"));
fprintf (stream, _("\ fprintf (stream, _("\
-mcom generate code for Power/PowerPC common instructions\n")); -mcom generate code for Power/PowerPC common instructions\n"));

3
include/opcode/ppc.h
View File

@ -237,6 +237,9 @@ extern const unsigned int spe2_num_opcodes;
/* Opcode is only supported by power10 architecture. */ /* Opcode is only supported by power10 architecture. */
#define PPC_OPCODE_POWER10 0x400000000000ull #define PPC_OPCODE_POWER10 0x400000000000ull
/* Opcode is only supported by SVP64 extensions (LibreSOC architecture). */
#define PPC_OPCODE_SVP64 0x800000000000ull
/* A macro to extract the major opcode from an instruction. */ /* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f) #define PPC_OP(i) (((i) >> 26) & 0x3f)

5
opcodes/ppc-dis.c
View File

@ -200,6 +200,11 @@ struct ppc_mopt ppc_opts[] = {
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
| PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
0 }, 0 },
{ "libresoc",(PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
| PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_SVP64),
0 },
{ "future", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 { "future", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9

1
opcodes/ppc-opc.c
View File

@ -4832,6 +4832,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
#define PPCHTM PPC_OPCODE_POWER8 #define PPCHTM PPC_OPCODE_POWER8
#define E200Z4 PPC_OPCODE_E200Z4 #define E200Z4 PPC_OPCODE_E200Z4
#define PPCLSP PPC_OPCODE_LSP #define PPCLSP PPC_OPCODE_LSP
#define SVP64 PPC_OPCODE_SVP64
/* Used to mark extended mnemonic in deprecated field so that -Mraw /* Used to mark extended mnemonic in deprecated field so that -Mraw
won't use this variant in disassembly. */ won't use this variant in disassembly. */
#define EXT PPC_OPCODE_RAW #define EXT PPC_OPCODE_RAW