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x86: consolidate tracking of MMX register use

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Just like for XMM/YMM/ZMM don't key this to any Cpu* flags. Instead
include the two special insns (not having register operands) explicitly.
This commit is contained in:
Jan Beulich
2019-12-04 10:43:50 +01:00
parent 77ad80922b
commit 319ff62c8a
2 changed files with 8 additions and 9 deletions
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5
gas/ChangeLog
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@ -1,3 +1,8 @@
2019-12-04 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (output_insn): Don't consider Cpu* settings
when setting GNU_PROPERTY_X86_FEATURE_2_MMX.
2019-12-04 Jan Beulich <jbeulich@suse.com> 2019-12-04 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/movdir.s: Add Intel syntax case with * testsuite/gas/i386/movdir.s: Add Intel syntax case with

12
gas/config/tc-i386.c
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@ -8259,15 +8259,9 @@ output_insn (void)
|| i.tm.cpu_flags.bitfield.cpu687 || i.tm.cpu_flags.bitfield.cpu687
|| i.tm.cpu_flags.bitfield.cpufisttp) || i.tm.cpu_flags.bitfield.cpufisttp)
x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87;
/* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor if (i.has_regmmx
Xfence instructions. */ || i.tm.base_opcode == 0xf77 /* emms */
if (i.tm.base_opcode != 0xf18 || i.tm.base_opcode == 0xf0e /* femms */)
&& i.tm.base_opcode != 0xf0d
&& i.tm.base_opcode != 0xfaef8
&& (i.has_regmmx
|| i.tm.cpu_flags.bitfield.cpummx
|| i.tm.cpu_flags.bitfield.cpua3dnow
|| i.tm.cpu_flags.bitfield.cpua3dnowa))
x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX;
if (i.has_regxmm) if (i.has_regxmm)
x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM;