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Update description of AArch64 assembler directives.

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gas	* doc/c-aarch64.texi (AArch64 Directives): Add descriptions of
	.cpu, .dword, .even, .inst. .tlsdescadd, .tlsdesccall,
	.tlsdescldr and .xword directives.
This commit is contained in:
Nick Clifton
2016-03-18 17:30:12 +00:00
parent 87bba7a5e0
commit 30fab42184
2 changed files with 45 additions and 4 deletions
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4
gas/ChangeLog
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@ -1,5 +1,9 @@
2016-03-18 Nick Clifton <nickc@redhat.com> 2016-03-18 Nick Clifton <nickc@redhat.com>
* doc/c-aarch64.texi (AArch64 Directives): Add descriptions of
.cpu, .dword, .even, .inst. .tlsdescadd, .tlsdesccall,
.tlsdescldr and .xword directives.
PR target/19721 PR target/19721
* testsuite/gas/aarch64/pr19721.s: New test source file. * testsuite/gas/aarch64/pr19721.s: New test source file.
* testsuite/gas/aarch64/pr19721.d: New test driver file. * testsuite/gas/aarch64/pr19721.d: New test driver file.

45
gas/doc/c-aarch64.texi
View File

@ -273,12 +273,35 @@ incrementally to the architecture being compiled for.
This directive switches to the @code{.bss} section. This directive switches to the @code{.bss} section.
@c CCCCCCCCCCCCCCCCCCCCCCCCCC @c CCCCCCCCCCCCCCCCCCCCCCCCCC
@cindex @code{.cpu} directive, AArch64
@item .cpu @var{name}
Set the target processor. Valid values for @var{name} are the same as
those accepted by the @option{-mcpu=} command line option.
@c DDDDDDDDDDDDDDDDDDDDDDDDDD @c DDDDDDDDDDDDDDDDDDDDDDDDDD
@cindex @code{.dword} directive, AArch64
@item .dword @var{expressions}
The @code{.dword} directive produces 64 bit values.
@c EEEEEEEEEEEEEEEEEEEEEEEEEE @c EEEEEEEEEEEEEEEEEEEEEEEEEE
@cindex @code{.even} directive, AArch64
@item .even
The @code{.even} directive aligns the output on the next even byte
boundary.
@c FFFFFFFFFFFFFFFFFFFFFFFFFF @c FFFFFFFFFFFFFFFFFFFFFFFFFF
@c GGGGGGGGGGGGGGGGGGGGGGGGGG @c GGGGGGGGGGGGGGGGGGGGGGGGGG
@c HHHHHHHHHHHHHHHHHHHHHHHHHH @c HHHHHHHHHHHHHHHHHHHHHHHHHH
@c IIIIIIIIIIIIIIIIIIIIIIIIII @c IIIIIIIIIIIIIIIIIIIIIIIIII
@cindex @code{.inst} directive, AArch64
@item .inst @var{expressions}
Inserts the expressions into the output as if they were instructions,
rather than data.
@c JJJJJJJJJJJJJJJJJJJJJJJJJJ @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
@c KKKKKKKKKKKKKKKKKKKKKKKKKK @c KKKKKKKKKKKKKKKKKKKKKKKKKK
@c LLLLLLLLLLLLLLLLLLLLLLLLLL @c LLLLLLLLLLLLLLLLLLLLLLLLLL
@ -324,6 +347,18 @@ example:
@c TTTTTTTTTTTTTTTTTTTTTTTTTT @c TTTTTTTTTTTTTTTTTTTTTTTTTT
@cindex @code{.tlsdescadd} directive, AArch64
@item @code{.tlsdescadd}
Emits a TLSDESC_ADD reloc on the next instruction.
@cindex @code{.tlsdesccall} directive, AArch64
@item @code{.tlsdesccall}
Emits a TLSDESC_CALL reloc on the next instruction.
@cindex @code{.tlsdescldr} directive, AArch64
@item @code{.tlsdescldr}
Emits a TLSDESC_LDR reloc on the next instruction.
@c UUUUUUUUUUUUUUUUUUUUUUUUUU @c UUUUUUUUUUUUUUUUUUUUUUUUUU
@cindex @code{.unreq} directive, AArch64 @cindex @code{.unreq} directive, AArch64
@ -344,12 +379,14 @@ should only be done if it is really necessary.
@c WWWWWWWWWWWWWWWWWWWWWWWWWW @c WWWWWWWWWWWWWWWWWWWWWWWWWW
@c XXXXXXXXXXXXXXXXXXXXXXXXXX @c XXXXXXXXXXXXXXXXXXXXXXXXXX
@c YYYYYYYYYYYYYYYYYYYYYYYYYY
@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
@cindex @code{.xword} directive, AArch64 @cindex @code{.xword} directive, AArch64
@item .xword @item .xword @var{expressions}
The @code{.xword} directive produces 64 bit values. The @code{.xword} directive produces 64 bit values. This is the same
as the @code{.dword} directive.
@c YYYYYYYYYYYYYYYYYYYYYYYYYY
@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
@end table @end table