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import gdb-1999-10-04 snapshot

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This commit is contained in:
Jason Molenda
1999-10-05 23:13:56 +00:00
parent 3e9c42873e
commit 2acceee218
112 changed files with 2316 additions and 855 deletions
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11
sim/m32r/ChangeLog
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@ -1,3 +1,14 @@
1999-09-29 Doug Evans <devans@casey.cygnus.com>
* mloop.in: Update call to sim_engine_invalid_insn.
* sem.c,sem-switch.c: Rebuild.
* traps.c (sim_engine_invalid_insn): New arg `vpc'. Change type of
result to SEM_PC. Return vpc.
Wed Sep 29 14:47:20 1999 Dave Brolley <brolley@cygnus.com>
* traps.c (sim_engine_invalid_insn): Return PC.
Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.

2
sim/m32r/mloop.in
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@ -253,7 +253,7 @@ cat <<EOF
{
/* ??? Defer signalling to execution. */
if ((insn & 0x7fff) != 0x7000) /* parallel nops are ok */
sim_engine_invalid_insn (current_cpu, pc - 2);
sim_engine_invalid_insn (current_cpu, pc - 2, 0);
/* There's no point in processing parallel nops in fast mode.
We might as well do this test since we've already tested
that we have a parallel nop. */

14
sim/m32r/sem-switch.c
View File

@ -204,13 +204,15 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
#if WITH_SCACHE
/* Update the recorded pc in the cpu state struct. */
/* Update the recorded pc in the cpu state struct.
Only necessary for WITH_SCACHE case, but to avoid the
conditional compilation .... */
SET_H_PC (pc);
#endif
sim_engine_invalid_insn (current_cpu, pc);
sim_io_error (CPU_STATE (current_cpu), "invalid insn not handled\n");
/* NOTREACHED */
/* Virtual insns have zero size. Overwrite vpc with address of next insn
using the default-insn-bitsize spec. When executing insns in parallel
we may want to queue the fault and continue execution. */
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
}
#undef FLD

18
sim/m32r/sem.c
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@ -55,13 +55,15 @@ SEM_FN_NAME (m32rbf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
#if WITH_SCACHE
/* Update the recorded pc in the cpu state struct. */
/* Update the recorded pc in the cpu state struct.
Only necessary for WITH_SCACHE case, but to avoid the
conditional compilation .... */
SET_H_PC (pc);
#endif
sim_engine_invalid_insn (current_cpu, pc);
sim_io_error (CPU_STATE (current_cpu), "invalid insn not handled\n");
/* NOTREACHED */
/* Virtual insns have zero size. Overwrite vpc with address of next insn
using the default-insn-bitsize spec. When executing insns in parallel
we may want to queue the fault and continue execution. */
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
}
return vpc;
@ -2675,7 +2677,9 @@ SEM_FN_NAME (m32rbf,init_idesc_table) (SIM_CPU *current_cpu)
for (sf = &sem_fns[0]; sf->fn != 0; ++sf)
{
int valid_p = CGEN_INSN_MACH_HAS_P (idesc_table[sf->index].idata, mach_num);
const CGEN_INSN *insn = idesc_table[sf->index].idata;
int valid_p = (CGEN_INSN_VIRTUAL_P (insn)
|| CGEN_INSN_MACH_HAS_P (insn, mach_num));
#if FAST_P
if (valid_p)
idesc_table[sf->index].sem_fast = sf->fn;

9
sim/m32r/traps.c
View File

@ -21,10 +21,12 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "sim-main.h"
#include "targ-vals.h"
/* The semantic code invokes this for invalid (unrecognized) instructions. */
/* The semantic code invokes this for invalid (unrecognized) instructions.
CIA is the address with the invalid insn.
VPC is the virtual pc of the following insn. */
void
sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia)
SEM_PC
sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
{
SIM_DESC sd = CPU_STATE (current_cpu);
@ -46,6 +48,7 @@ sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia)
else
#endif
sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
return vpc;
}
/* Process an address exception. */