[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions

This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)

This patch adds the prediction restriction instructions (that is, cfp,
dvp, cpp). These instructions are retrospectively made optional for
all versions of the architecture from ARMv8.0 to ARMv8.4 and is
mandatory from ARMv8.5. Hence adding a new +predres which can be used
by the older architectures.

*** include/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.
	(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default.
	(aarch64_opnd): Add AARCH64_OPND_SYSREG_SR.
	(aarch64_sys_regs_sr): Declare new table.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-dis.c (aarch64_ext_sysins_op): Add case for
	AARCH64_OPND_SYSREG_SR.
	* aarch64-opc.c (aarch64_print_operand): Likewise.
	(aarch64_sys_regs_sr): Define table.
	(aarch64_sys_ins_reg_supported_p): Check for RCTX with
	AARCH64_FEATURE_PREDRES.
	* aarch64-tbl.h (aarch64_feature_predres): New.
	(PREDRES, PREDRES_INSN): New.
	(aarch64_opcode_table): Add entries for cfp, dvp and cpp.
	(AARCH64_OPERANDS): Add new description for SYSREG_SR.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

*** gas/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New.
	(parse_operands): Add entry for AARCH64_OPND_SYSREG_SR.
	(md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh
	with aarch64_sys_regs_sr.
	(aarch64_features): Add new "predres" option for older
	architectures.
	* doc/c-aarch64.texi: Document the same.
	* testsuite/gas/aarch64/sysreg-4.s: New.
	* testsuite/gas/aarch64/sysreg-4.d: New.
	* testsuite/gas/aarch64/illegal-sysreg-4.d: New.
	* testsuite/gas/aarch64/illegal-sysreg-4.l: New.
	* testsuite/gas/aarch64/predres.s: New.
	* testsuite/gas/aarch64/predres.d: New.

gas/ChangeLog

@@ -1,3 +1,19 @@
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+	* config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New.
+	(parse_operands): Add entry for AARCH64_OPND_SYSREG_SR.
+	(md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh
+	with aarch64_sys_regs_sr.
+	(aarch64_features): Add new "predres" option for older
+	architectures.
+	* doc/c-aarch64.texi: Document the same.
+	* testsuite/gas/aarch64/sysreg-4.s: New.
+	* testsuite/gas/aarch64/sysreg-4.d: New.
+	* testsuite/gas/aarch64/illegal-sysreg-4.d: New.
+	* testsuite/gas/aarch64/illegal-sysreg-4.l: New.
+	* testsuite/gas/aarch64/predres.s: New.
+	* testsuite/gas/aarch64/predres.d: New.
+
 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 
 	* config/tc-aarch64.c (aarch64_features): Add new "sb" option

gas/config/tc-aarch64.c

@@ -462,6 +462,7 @@ static struct hash_control *aarch64_sys_regs_ic_hsh;
 static struct hash_control *aarch64_sys_regs_dc_hsh;
 static struct hash_control *aarch64_sys_regs_at_hsh;
 static struct hash_control *aarch64_sys_regs_tlbi_hsh;
+static struct hash_control *aarch64_sys_regs_sr_hsh;
 static struct hash_control *aarch64_reg_hsh;
 static struct hash_control *aarch64_barrier_opt_hsh;
 static struct hash_control *aarch64_nzcv_hsh;
@@ -6422,14 +6423,22 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	  inst.base.operands[i].sysins_op =
 	    parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh);
 	  goto sys_reg_ins;
+
 	case AARCH64_OPND_SYSREG_DC:
 	  inst.base.operands[i].sysins_op =
 	    parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh);
 	  goto sys_reg_ins;
+
 	case AARCH64_OPND_SYSREG_AT:
 	  inst.base.operands[i].sysins_op =
 	    parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh);
 	  goto sys_reg_ins;
+
+	case AARCH64_OPND_SYSREG_SR:
+	  inst.base.operands[i].sysins_op =
+	    parse_sys_ins_reg (&str, aarch64_sys_regs_sr_hsh);
+	  goto sys_reg_ins;
+
 	case AARCH64_OPND_SYSREG_TLBI:
 	  inst.base.operands[i].sysins_op =
 	    parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);
@@ -8439,6 +8448,7 @@ md_begin (void)
       || (aarch64_sys_regs_dc_hsh = hash_new ()) == NULL
       || (aarch64_sys_regs_at_hsh = hash_new ()) == NULL
       || (aarch64_sys_regs_tlbi_hsh = hash_new ()) == NULL
+      || (aarch64_sys_regs_sr_hsh = hash_new ()) == NULL
       || (aarch64_reg_hsh = hash_new ()) == NULL
       || (aarch64_barrier_opt_hsh = hash_new ()) == NULL
       || (aarch64_nzcv_hsh = hash_new ()) == NULL
@@ -8477,6 +8487,11 @@ md_begin (void)
 			 aarch64_sys_regs_tlbi[i].name,
 			 (void *) (aarch64_sys_regs_tlbi + i));
 
+  for (i = 0; aarch64_sys_regs_sr[i].name != NULL; i++)
+    checked_hash_insert (aarch64_sys_regs_sr_hsh,
+			 aarch64_sys_regs_sr[i].name,
+			 (void *) (aarch64_sys_regs_sr + i));
+
   for (i = 0; i < ARRAY_SIZE (reg_names); i++)
     checked_hash_insert (aarch64_reg_hsh, reg_names[i].name,
 			 (void *) (reg_names + i));
@@ -8749,6 +8764,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
 			AARCH64_ARCH_NONE},
   {"sb",		AARCH64_FEATURE (AARCH64_FEATURE_SB, 0),
 			AARCH64_ARCH_NONE},
+  {"predres",		AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0),
+			AARCH64_ARCH_NONE},
   {"aes",		AARCH64_FEATURE (AARCH64_FEATURE_AES, 0),
 			AARCH64_ARCH_NONE},
   {"sm4",		AARCH64_FEATURE (AARCH64_FEATURE_SM4, 0),

gas/doc/c-aarch64.texi

@@ -183,6 +183,8 @@ automatically cause those extensions to be disabled.
  This implies @code{fp16}.
 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
  @tab Enable the speculation barrier instruction sb.
+@item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
+ @tab Enable the Execution and Data and Prediction instructions.
 @end multitable
 
 @node AArch64 Syntax

gas/testsuite/gas/aarch64/illegal-sysreg-4.d

@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sysreg-4.s
+#error_output: illegal-sysreg-4.l

gas/testsuite/gas/aarch64/illegal-sysreg-4.l

@@ -0,0 +1,7 @@
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
+[^:]*:[0-9]+: Error: selected processor does not support `cfp rctx,x1'
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
+[^:]*:[0-9]+: Error: selected processor does not support `dvp rctx,x2'
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
+[^:]*:[0-9]+: Error: selected processor does not support `cpp rctx,x3'

gas/testsuite/gas/aarch64/predres.d

@@ -0,0 +1,11 @@
+#as: -march=armv8-a+predres
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d50b7381 	cfp	rctx, x1
+.*:	d50b73a2 	dvp	rctx, x2
+.*:	d50b73e3 	cpp	rctx, x3

gas/testsuite/gas/aarch64/predres.s

@@ -0,0 +1,5 @@
+/* File to test the +predres option.  */
+func:
+	cfp rctx, x1
+	dvp rctx, x2
+	cpp rctx, x3

gas/testsuite/gas/aarch64/sysreg-4.d

@@ -0,0 +1,12 @@
+#source: sysreg-4.s
+#as: -march=armv8.5-a
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d50b7381 	cfp	rctx, x1
+.*:	d50b73a2 	dvp	rctx, x2
+.*:	d50b73e3 	cpp	rctx, x3

gas/testsuite/gas/aarch64/sysreg-4.s

@@ -0,0 +1,5 @@
+/* sysreg-4.s Test file for ARMv8.5 system registers.  */
+func:
+	cfp rctx, x1
+	dvp rctx, x2
+	cpp rctx, x3

include/ChangeLog

@@ -1,3 +1,10 @@
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.
+	(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default.
+	(aarch64_opnd): Add AARCH64_OPND_SYSREG_SR.
+	(aarch64_sys_regs_sr): Declare new table.
+
 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 
 	* opcode/aarch64.h (AARCH64_FEATURE_SB): New.

include/opcode/aarch64.h

@@ -70,6 +70,8 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_FRINTTS		0x8000000000ULL
 /* SB instruction.  */
 #define AARCH64_FEATURE_SB		0x10000000000ULL
+/* Execution and Data Prediction Restriction instructions.  */
+#define AARCH64_FEATURE_PREDRES		0x20000000000ULL
 
 /* Architectures are the sum of the base and extensions.  */
 #define AARCH64_ARCH_V8		AARCH64_FEATURE (AARCH64_FEATURE_V8, \
@@ -97,7 +99,8 @@ typedef uint32_t aarch64_insn;
 						 AARCH64_FEATURE_V8_5   \
 						 | AARCH64_FEATURE_FLAGMANIP \
 						 | AARCH64_FEATURE_FRINTTS \
-						 | AARCH64_FEATURE_SB)
+						 | AARCH64_FEATURE_SB   \
+						 | AARCH64_FEATURE_PREDRES)
 
 
 #define AARCH64_ARCH_NONE	AARCH64_FEATURE (0, 0)
@@ -272,6 +275,7 @@ enum aarch64_opnd
   AARCH64_OPND_SYSREG_DC,	/* System register <dc_op> operand.  */
   AARCH64_OPND_SYSREG_IC,	/* System register <ic_op> operand.  */
   AARCH64_OPND_SYSREG_TLBI,	/* System register <tlbi_op> operand.  */
+  AARCH64_OPND_SYSREG_SR,	/* System register RCTX operand.  */
   AARCH64_OPND_BARRIER,		/* Barrier operand.  */
   AARCH64_OPND_BARRIER_ISB,	/* Barrier operand for ISB.  */
   AARCH64_OPND_PRFOP,		/* Prefetch operation.  */
@@ -915,6 +919,7 @@ extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
+extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
 
 /* Shift/extending operator kinds.
    N.B. order is important; keep aarch64_operand_modifiers synced.  */

opcodes/ChangeLog

@@ -1,3 +1,19 @@
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+	* aarch64-dis.c (aarch64_ext_sysins_op): Add case for
+	AARCH64_OPND_SYSREG_SR.
+	* aarch64-opc.c (aarch64_print_operand): Likewise.
+	(aarch64_sys_regs_sr): Define table.
+	(aarch64_sys_ins_reg_supported_p): Check for RCTX with
+	AARCH64_FEATURE_PREDRES.
+	* aarch64-tbl.h (aarch64_feature_predres): New.
+	(PREDRES, PREDRES_INSN): New.
+	(aarch64_opcode_table): Add entries for cfp, dvp and cpp.
+	(AARCH64_OPERANDS): Add new description for SYSREG_SR.
+	* aarch64-asm-2.c: Regenerate.
+	* aarch64-dis-2.c: Regenerate.
+	* aarch64-opc-2.c: Regenerate.
+
 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 
 	* aarch64-tbl.h (aarch64_feature_sb): New.

opcodes/aarch64-asm-2.c

@@ -422,14 +422,14 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
     case 1162:	/* movz */
       value = 1162;	/* --> movz.  */
       break;
-    case 1205:	/* autibsp */
+    case 1208:	/* autibsp */
-    case 1204:	/* autibz */
+    case 1207:	/* autibz */
-    case 1203:	/* autiasp */
+    case 1206:	/* autiasp */
-    case 1202:	/* autiaz */
+    case 1205:	/* autiaz */
-    case 1201:	/* pacibsp */
+    case 1204:	/* pacibsp */
-    case 1200:	/* pacibz */
+    case 1203:	/* pacibz */
-    case 1199:	/* paciasp */
+    case 1202:	/* paciasp */
-    case 1198:	/* paciaz */
+    case 1201:	/* paciaz */
     case 1182:	/* psb */
     case 1181:	/* esb */
     case 1180:	/* autib1716 */
@@ -452,6 +452,9 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
     case 1184:	/* dsb */
       value = 1184;	/* --> dsb.  */
       break;
+    case 1197:	/* cpp */
+    case 1196:	/* dvp */
+    case 1195:	/* cfp */
     case 1194:	/* tlbi */
     case 1193:	/* ic */
     case 1192:	/* dc */
@@ -459,124 +462,124 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
     case 1190:	/* sys */
       value = 1190;	/* --> sys.  */
       break;
-    case 2003:	/* bic */
+    case 2006:	/* bic */
-    case 1253:	/* and */
+    case 1256:	/* and */
-      value = 1253;	/* --> and.  */
+      value = 1256;	/* --> and.  */
+      break;
+    case 1239:	/* mov */
+    case 1258:	/* and */
+      value = 1258;	/* --> and.  */
+      break;
+    case 1243:	/* movs */
+    case 1259:	/* ands */
+      value = 1259;	/* --> ands.  */
+      break;
+    case 2007:	/* cmple */
+    case 1294:	/* cmpge */
+      value = 1294;	/* --> cmpge.  */
+      break;
+    case 2010:	/* cmplt */
+    case 1297:	/* cmpgt */
+      value = 1297;	/* --> cmpgt.  */
+      break;
+    case 2008:	/* cmplo */
+    case 1299:	/* cmphi */
+      value = 1299;	/* --> cmphi.  */
+      break;
+    case 2009:	/* cmpls */
+    case 1302:	/* cmphs */
+      value = 1302;	/* --> cmphs.  */
       break;
     case 1236:	/* mov */
-    case 1255:	/* and */
+    case 1324:	/* cpy */
-      value = 1255;	/* --> and.  */
+      value = 1324;	/* --> cpy.  */
       break;
-    case 1240:	/* movs */
-    case 1256:	/* ands */
-      value = 1256;	/* --> ands.  */
-      break;
-    case 2004:	/* cmple */
-    case 1291:	/* cmpge */
-      value = 1291;	/* --> cmpge.  */
-      break;
-    case 2007:	/* cmplt */
-    case 1294:	/* cmpgt */
-      value = 1294;	/* --> cmpgt.  */
-      break;
-    case 2005:	/* cmplo */
-    case 1296:	/* cmphi */
-      value = 1296;	/* --> cmphi.  */
-      break;
-    case 2006:	/* cmpls */
-    case 1299:	/* cmphs */
-      value = 1299;	/* --> cmphs.  */
-      break;
-    case 1233:	/* mov */
-    case 1321:	/* cpy */
-      value = 1321;	/* --> cpy.  */
-      break;
-    case 1235:	/* mov */
-    case 1322:	/* cpy */
-      value = 1322;	/* --> cpy.  */
-      break;
-    case 2014:	/* fmov */
     case 1238:	/* mov */
-    case 1323:	/* cpy */
+    case 1325:	/* cpy */
-      value = 1323;	/* --> cpy.  */
+      value = 1325;	/* --> cpy.  */
       break;
-    case 1228:	/* mov */
+    case 2017:	/* fmov */
-    case 1335:	/* dup */
+    case 1241:	/* mov */
-      value = 1335;	/* --> dup.  */
+    case 1326:	/* cpy */
-      break;
+      value = 1326;	/* --> cpy.  */
-    case 1230:	/* mov */
-    case 1227:	/* mov */
-    case 1336:	/* dup */
-      value = 1336;	/* --> dup.  */
-      break;
-    case 2013:	/* fmov */
-    case 1232:	/* mov */
-    case 1337:	/* dup */
-      value = 1337;	/* --> dup.  */
       break;
     case 1231:	/* mov */
-    case 1338:	/* dupm */
+    case 1338:	/* dup */
-      value = 1338;	/* --> dupm.  */
+      value = 1338;	/* --> dup.  */
       break;
-    case 2008:	/* eon */
+    case 1233:	/* mov */
-    case 1340:	/* eor */
+    case 1230:	/* mov */
-      value = 1340;	/* --> eor.  */
+    case 1339:	/* dup */
+      value = 1339;	/* --> dup.  */
       break;
-    case 1241:	/* not */
+    case 2016:	/* fmov */
-    case 1342:	/* eor */
+    case 1235:	/* mov */
-      value = 1342;	/* --> eor.  */
+    case 1340:	/* dup */
+      value = 1340;	/* --> dup.  */
       break;
-    case 1242:	/* nots */
+    case 1234:	/* mov */
-    case 1343:	/* eors */
+    case 1341:	/* dupm */
-      value = 1343;	/* --> eors.  */
+      value = 1341;	/* --> dupm.  */
       break;
-    case 2009:	/* facle */
+    case 2011:	/* eon */
-    case 1348:	/* facge */
+    case 1343:	/* eor */
-      value = 1348;	/* --> facge.  */
+      value = 1343;	/* --> eor.  */
       break;
-    case 2010:	/* faclt */
+    case 1244:	/* not */
-    case 1349:	/* facgt */
+    case 1345:	/* eor */
-      value = 1349;	/* --> facgt.  */
+      value = 1345;	/* --> eor.  */
       break;
-    case 2011:	/* fcmle */
+    case 1245:	/* nots */
-    case 1362:	/* fcmge */
+    case 1346:	/* eors */
-      value = 1362;	/* --> fcmge.  */
+      value = 1346;	/* --> eors.  */
       break;
-    case 2012:	/* fcmlt */
+    case 2012:	/* facle */
-    case 1364:	/* fcmgt */
+    case 1351:	/* facge */
-      value = 1364;	/* --> fcmgt.  */
+      value = 1351;	/* --> facge.  */
       break;
-    case 1225:	/* fmov */
+    case 2013:	/* faclt */
-    case 1370:	/* fcpy */
+    case 1352:	/* facgt */
-      value = 1370;	/* --> fcpy.  */
+      value = 1352;	/* --> facgt.  */
       break;
-    case 1224:	/* fmov */
+    case 2014:	/* fcmle */
-    case 1393:	/* fdup */
+    case 1365:	/* fcmge */
-      value = 1393;	/* --> fdup.  */
+      value = 1365;	/* --> fcmge.  */
       break;
-    case 1226:	/* mov */
+    case 2015:	/* fcmlt */
-    case 1724:	/* orr */
+    case 1367:	/* fcmgt */
-      value = 1724;	/* --> orr.  */
+      value = 1367;	/* --> fcmgt.  */
       break;
-    case 2015:	/* orn */
+    case 1228:	/* fmov */
-    case 1725:	/* orr */
+    case 1373:	/* fcpy */
-      value = 1725;	/* --> orr.  */
+      value = 1373;	/* --> fcpy.  */
+      break;
+    case 1227:	/* fmov */
+    case 1396:	/* fdup */
+      value = 1396;	/* --> fdup.  */
       break;
     case 1229:	/* mov */
     case 1727:	/* orr */
       value = 1727;	/* --> orr.  */
       break;
-    case 1239:	/* movs */
+    case 2018:	/* orn */
-    case 1728:	/* orrs */
+    case 1728:	/* orr */
-      value = 1728;	/* --> orrs.  */
+      value = 1728;	/* --> orr.  */
       break;
-    case 1234:	/* mov */
+    case 1232:	/* mov */
-    case 1790:	/* sel */
+    case 1730:	/* orr */
-      value = 1790;	/* --> sel.  */
+      value = 1730;	/* --> orr.  */
+      break;
+    case 1242:	/* movs */
+    case 1731:	/* orrs */
+      value = 1731;	/* --> orrs.  */
       break;
     case 1237:	/* mov */
-    case 1791:	/* sel */
+    case 1793:	/* sel */
-      value = 1791;	/* --> sel.  */
+      value = 1793;	/* --> sel.  */
+      break;
+    case 1240:	/* mov */
+    case 1794:	/* sel */
+      value = 1794;	/* --> sel.  */
       break;
     default: return NULL;
     }
@@ -619,7 +622,6 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 27:
     case 28:
     case 29:
-    case 153:
     case 154:
     case 155:
     case 156:
@@ -629,7 +631,7 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 160:
     case 161:
     case 162:
-    case 175:
+    case 163:
     case 176:
     case 177:
     case 178:
@@ -638,8 +640,9 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 181:
     case 182:
     case 183:
-    case 187:
+    case 184:
-    case 190:
+    case 188:
+    case 191:
       return aarch64_ins_regno (self, info, code, inst, errors);
     case 13:
       return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -651,7 +654,7 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 31:
     case 32:
     case 33:
-    case 192:
+    case 193:
       return aarch64_ins_reglane (self, info, code, inst, errors);
     case 34:
       return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -683,9 +686,8 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 77:
     case 78:
     case 79:
-    case 150:
+    case 151:
-    case 152:
+    case 153:
-    case 167:
     case 168:
     case 169:
     case 170:
@@ -693,6 +695,7 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 172:
     case 173:
     case 174:
+    case 175:
       return aarch64_ins_imm (self, info, code, inst, errors);
     case 42:
     case 43:
@@ -702,10 +705,10 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 46:
       return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
     case 50:
-    case 141:
+    case 142:
       return aarch64_ins_fpimm (self, info, code, inst, errors);
     case 65:
-    case 148:
+    case 149:
       return aarch64_ins_limm (self, info, code, inst, errors);
     case 66:
       return aarch64_ins_aimm (self, info, code, inst, errors);
@@ -715,10 +718,10 @@ aarch64_insert_operand (const aarch64_operand *self,
       return aarch64_ins_fbits (self, info, code, inst, errors);
     case 70:
     case 71:
-    case 146:
+    case 147:
       return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
     case 72:
-    case 145:
+    case 146:
       return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
     case 73:
     case 74:
@@ -748,31 +751,31 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 93:
     case 94:
     case 95:
-      return aarch64_ins_sysins_op (self, info, code, inst, errors);
     case 96:
+      return aarch64_ins_sysins_op (self, info, code, inst, errors);
     case 97:
-      return aarch64_ins_barrier (self, info, code, inst, errors);
     case 98:
-      return aarch64_ins_prfop (self, info, code, inst, errors);
+      return aarch64_ins_barrier (self, info, code, inst, errors);
     case 99:
-      return aarch64_ins_hint (self, info, code, inst, errors);
+      return aarch64_ins_prfop (self, info, code, inst, errors);
     case 100:
-      return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
+      return aarch64_ins_hint (self, info, code, inst, errors);
     case 101:
+      return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
     case 102:
     case 103:
     case 104:
-      return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
     case 105:
-      return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
     case 106:
-      return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
     case 107:
+      return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
     case 108:
     case 109:
     case 110:
-      return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
     case 111:
+      return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
     case 112:
     case 113:
     case 114:
@@ -785,8 +788,8 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 121:
     case 122:
     case 123:
-      return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
     case 124:
+      return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
     case 125:
     case 126:
     case 127:
@@ -794,48 +797,49 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 129:
     case 130:
     case 131:
-      return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
     case 132:
+      return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
     case 133:
     case 134:
     case 135:
-      return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
     case 136:
-      return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
     case 137:
-      return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
     case 138:
-      return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
     case 139:
-      return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
     case 140:
+      return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+    case 141:
       return aarch64_ins_sve_asimm (self, info, code, inst, errors);
-    case 142:
-      return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
     case 143:
-      return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+      return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
     case 144:
+      return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+    case 145:
       return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
-    case 147:
+    case 148:
       return aarch64_ins_inv_limm (self, info, code, inst, errors);
-    case 149:
+    case 150:
       return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
-    case 151:
+    case 152:
       return aarch64_ins_sve_scale (self, info, code, inst, errors);
-    case 163:
     case 164:
-      return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
     case 165:
+      return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
     case 166:
+    case 167:
       return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
-    case 184:
     case 185:
     case 186:
+    case 187:
       return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
-    case 188:
-      return aarch64_ins_sve_index (self, info, code, inst, errors);
     case 189:
-    case 191:
+      return aarch64_ins_sve_index (self, info, code, inst, errors);
+    case 190:
+    case 192:
       return aarch64_ins_sve_reglist (self, info, code, inst, errors);
     default: assert (0); abort ();
     }

opcodes/aarch64-dis.c

@@ -1243,6 +1243,12 @@ aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
     case AARCH64_OPND_SYSREG_DC: sysins_ops = aarch64_sys_regs_dc; break;
     case AARCH64_OPND_SYSREG_IC: sysins_ops = aarch64_sys_regs_ic; break;
     case AARCH64_OPND_SYSREG_TLBI: sysins_ops = aarch64_sys_regs_tlbi; break;
+    case AARCH64_OPND_SYSREG_SR:
+	sysins_ops = aarch64_sys_regs_sr;
+	 /* Let's remove op2 for rctx.  Refer to comments in the definition of
+	    aarch64_sys_regs_sr[].  */
+	value = value & ~(0x7);
+	break;
     default: assert (0); return FALSE;
     }
 

opcodes/aarch64-opc-2.c

@@ -120,6 +120,7 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_DC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a data cache maintenance operation specifier"},
   {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_IC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an instruction cache maintenance operation specifier"},
   {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_TLBI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a TBL invalidation operation specifier"},
+  {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_SR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a Speculation Restriction option name (RCTX)"},
   {AARCH64_OPND_CLASS_SYSTEM, "BARRIER", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a barrier option name"},
   {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"},
   {AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"},
@@ -294,17 +295,17 @@ static const unsigned op_enum_table [] =
   389,
   411,
   413,
-  1229,
+  1232,
-  1234,
-  1227,
-  1226,
-  1230,
   1237,
-  1239,
+  1230,
+  1229,
+  1233,
   1240,
-  1236,
   1242,
-  1241,
+  1243,
+  1239,
+  1245,
+  1244,
   129,
 };
 

opcodes/aarch64-opc.c

@@ -3630,6 +3630,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_SYSREG_DC:
     case AARCH64_OPND_SYSREG_IC:
     case AARCH64_OPND_SYSREG_TLBI:
+    case AARCH64_OPND_SYSREG_SR:
       snprintf (buf, size, "%s", opnd->sysins_op->name);
       break;
 
@@ -4458,6 +4459,17 @@ const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
     { 0,       CPENS(0,0,0,0), 0 }
 };
 
+const aarch64_sys_ins_reg aarch64_sys_regs_sr[] =
+{
+    /* RCTX is somewhat unique in a way that it has different values
+       (op2) based on the instruction in which it is used (cfp/dvp/cpp).
+       Thus op2 is masked out and instead encoded directly in the
+       aarch64_opcode_table entries for the respective instructions.  */
+    { "rctx",   CPENS(3,C7,C3,0), F_HASXT | F_ARCHEXT | F_REG_WRITE}, /* WO */
+
+    { 0,       CPENS(0,0,0,0), 0 }
+};
+
 bfd_boolean
 aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
 {
@@ -4482,6 +4494,11 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
     return FALSE;
 
+  /* CFP/DVP/CPP RCTX : Value are from aarch64_sys_regs_sr. */
+  if (reg->value == CPENS (3, C7, C3, 0)
+      && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PREDRES))
+    return FALSE;
+
   return TRUE;
 }
 

opcodes/aarch64-tbl.h

@@ -2167,6 +2167,8 @@ static const aarch64_feature_set aarch64_feature_frintts =
   AARCH64_FEATURE (AARCH64_FEATURE_FRINTTS, 0);
 static const aarch64_feature_set aarch64_feature_sb =
   AARCH64_FEATURE (AARCH64_FEATURE_SB, 0);
+static const aarch64_feature_set aarch64_feature_predres =
+  AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0);
 
 
 #define CORE		&aarch64_feature_v8
@@ -2199,6 +2201,7 @@ static const aarch64_feature_set aarch64_feature_sb =
 #define FLAGMANIP	&aarch64_feature_flagmanip
 #define FRINTTS		&aarch64_feature_frintts
 #define SB		&aarch64_feature_sb
+#define PREDRES		&aarch64_feature_predres
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2258,6 +2261,8 @@ static const aarch64_feature_set aarch64_feature_sb =
   { NAME, OPCODE, MASK, CLASS, 0, FRINTTS, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define SB_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, SB, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define PREDRES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, CLASS, 0, PREDRES, OPS, QUALS, FLAGS, 0, 0, NULL }
 
 struct aarch64_opcode aarch64_opcode_table[] =
 {
@@ -3529,6 +3534,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("dc",  0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS),
   CORE_INSN ("ic",  0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
   CORE_INSN ("tlbi",0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
+  PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
+  PREDRES_INSN ("dvp", 0xd50b73a0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
+  PREDRES_INSN ("cpp", 0xd50b73e0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
   CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, F_SYS_WRITE),
   CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, 0, OP5 (Rt, UIMM3_OP1, CRn, CRm, UIMM3_OP2), QL_SYSL, 0),
   CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, F_SYS_READ),
@@ -4611,6 +4619,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
       "an instruction cache maintenance operation specifier")		\
     Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(),				\
       "a TBL invalidation operation specifier")				\
+    Y(SYSTEM, sysins_op, "SYSREG_SR", 0, F(),				\
+      "a Speculation Restriction option name (RCTX)")			\
     Y(SYSTEM, barrier, "BARRIER", 0, F(),				\
       "a barrier option name")						\
     Y(SYSTEM, barrier, "BARRIER_ISB", 0, F(),				\