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Add support for TBM instructions.

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gas/

2011-01-17  Quentin Neill  <quentin.neill@amd.com>

	* config/tc-i386.c (cpu_arch): Add CPU_TBM_FLAGS.

	* doc/c-i386.texi (i386-TBM): New section.

opcodes/

2011-01-17  Quentin Neill  <quentin.neill@amd.com>

	* i386-dis.c (REG_XOP_TBM_01): New.
	(REG_XOP_TBM_02): New.
	(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
	(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
	entries, and add bextr instruction.

	* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
	(cpu_flags): Add CpuTBM.

	* i386-opc.h (CpuTBM) New.
	(i386_cpu_flags): Add bit cputbm.

	* i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
	blcs, blsfill, blsic, t1mskc, and tzmsk.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Regenerated

gas/testsuite

2011-01-17  Quentin Neill  <quentin.neill@amd.com>

	* gas/i386/tbm.s: New.
	* gas/i386/tbm.d: New.
	* gas/i386/tbm-intel.d: New.
	* gas/i386/x86-64-tbm.s: New.
	* gas/i386/x86-64-tbm.d: New.
	* gas/i386/x86-64-tbm-intel.d: New.
	* gas/i386/arch-10.d: Add tbm flag and TBM instruction pattern.
	* gas/i386/arch-10.s: Add a TBM instruction.
	* gas/i386/arch-10-1.l: Add TBM instruction pattern.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/x86-64-arch-2.s: Likewise.
	* gas/i386/x86-64-arch-2.d: Likewise.
This commit is contained in:
Quentin Neill
2011-01-17 18:40:36 +00:00
parent dc92e16124
commit 2a2a0f38e7
18 changed files with 131 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
opcodes/i386-dis.c
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@ -601,7 +601,9 @@ enum
REG_VEX_0FAE,
REG_VEX_0F38F3,
REG_XOP_LWPCB,
REG_XOP_LWP
REG_XOP_LWP,
REG_XOP_TBM_01,
REG_XOP_TBM_02
};
enum
@ -2779,6 +2781,27 @@ static const struct dis386 reg_table[][8] = {
{ "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
{ "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
},
/* REG_XOP_TBM_01 */
{
{ Bad_Opcode },
{ "blcfill", { { OP_LWP_E, 0 }, Ev } },
{ "blsfill", { { OP_LWP_E, 0 }, Ev } },
{ "blcs", { { OP_LWP_E, 0 }, Ev } },
{ "tzmsk", { { OP_LWP_E, 0 }, Ev } },
{ "blcic", { { OP_LWP_E, 0 }, Ev } },
{ "blsic", { { OP_LWP_E, 0 }, Ev } },
{ "t1mskc", { { OP_LWP_E, 0 }, Ev } },
},
/* REG_XOP_TBM_02 */
{
{ Bad_Opcode },
{ "blcmsk", { { OP_LWP_E, 0 }, Ev } },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ "blci", { { OP_LWP_E, 0 }, Ev } },
},
};
static const struct dis386 prefix_table[][4] = {
@ -6459,7 +6482,7 @@ static const struct dis386 xop_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
{ Bad_Opcode },
{ "bextr", { Gv, Ev, Iq } },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@ -6733,8 +6756,8 @@ static const struct dis386 xop_table[][256] = {
{
/* 00 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ REG_TABLE (REG_XOP_TBM_01) },
{ REG_TABLE (REG_XOP_TBM_02) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@ -7041,7 +7064,7 @@ static const struct dis386 xop_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
{ Bad_Opcode },
{ "bextr", { Gv, Ev, Iq } },
{ Bad_Opcode },
{ REG_TABLE (REG_XOP_LWP) },
{ Bad_Opcode },