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https://github.com/espressif/binutils-gdb.git
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sim: h8300: simplify h8300_reg_{fetch,store} funcs
We can leverage the cpu->regs array rather than going through the function helpers to get nice compact code. Further, fix up the return values: return -1 when we can't find a register (and let the caller write out warnings), return 2/4 when we actually write out that amount, and handle the zero reg.
This commit is contained in:
@ -1,3 +1,15 @@
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2015-12-30 Mike Frysinger <vapier@gentoo.org>
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* compile.c (h8300_reg_store): Delete sd. Change init_pointers to
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use CPU_STATE (cpu). Change h8_set_pc to cpu->pc. Return -1 and
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drop the printf if the default case. Change all the set func calls
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to use cpu->regs[rn] instead.
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(h8300_reg_store): Delete sd. Change init_pointers to
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use CPU_STATE (cpu). Change h8_get_pc to cpu->pc. Return -1 and
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drop the printf if the default case. Change all the get func calls
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to use cpu->regs[rn] instead. Add ZERO_REGNUM case. Return 2 and
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4 instead of -1 at the end.
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2015-12-30 Mike Frysinger <vapier@gentoo.org>
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2015-12-30 Mike Frysinger <vapier@gentoo.org>
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* compile.c (lvalue): Change sim_engine_set_run_state calls to
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* compile.c (lvalue): Change sim_engine_set_run_state calls to
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@ -4605,7 +4605,6 @@ sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
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static int
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static int
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h8300_reg_store (SIM_CPU *cpu, int rn, unsigned char *value, int length)
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h8300_reg_store (SIM_CPU *cpu, int rn, unsigned char *value, int length)
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{
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{
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SIM_DESC sd = CPU_STATE (cpu);
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int longval;
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int longval;
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int shortval;
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int shortval;
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int intval;
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int intval;
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@ -4613,17 +4612,17 @@ h8300_reg_store (SIM_CPU *cpu, int rn, unsigned char *value, int length)
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shortval = (value[0] << 8) | (value[1]);
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shortval = (value[0] << 8) | (value[1]);
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intval = h8300hmode ? longval : shortval;
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intval = h8300hmode ? longval : shortval;
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init_pointers (sd);
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init_pointers (CPU_STATE (cpu));
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switch (rn)
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switch (rn)
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{
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{
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case PC_REGNUM:
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case PC_REGNUM:
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if(h8300_normal_mode)
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if(h8300_normal_mode)
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h8_set_pc (sd, shortval); /* PC for Normal mode is 2 bytes */
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cpu->pc = shortval; /* PC for Normal mode is 2 bytes */
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else
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else
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h8_set_pc (sd, intval);
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cpu->pc = intval;
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break;
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break;
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default:
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default:
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sim_io_printf (sd, "sim_store_register: bad regnum %d.\n", rn);
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return -1;
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case R0_REGNUM:
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case R0_REGNUM:
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case R1_REGNUM:
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case R1_REGNUM:
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case R2_REGNUM:
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case R2_REGNUM:
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@ -4632,36 +4631,18 @@ h8300_reg_store (SIM_CPU *cpu, int rn, unsigned char *value, int length)
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case R5_REGNUM:
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case R5_REGNUM:
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case R6_REGNUM:
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case R6_REGNUM:
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case R7_REGNUM:
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case R7_REGNUM:
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h8_set_reg (sd, rn, intval);
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break;
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case CCR_REGNUM:
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case CCR_REGNUM:
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h8_set_ccr (sd, intval);
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break;
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case EXR_REGNUM:
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case EXR_REGNUM:
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h8_set_exr (sd, intval);
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break;
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case SBR_REGNUM:
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case SBR_REGNUM:
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h8_set_sbr (sd, intval);
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break;
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case VBR_REGNUM:
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case VBR_REGNUM:
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h8_set_vbr (sd, intval);
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break;
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case MACH_REGNUM:
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case MACH_REGNUM:
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h8_set_mach (sd, intval);
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break;
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case MACL_REGNUM:
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case MACL_REGNUM:
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h8_set_macl (sd, intval);
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cpu->regs[rn] = intval;
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break;
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break;
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case CYCLE_REGNUM:
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case CYCLE_REGNUM:
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h8_set_cycles (sd, longval);
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break;
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case INST_REGNUM:
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case INST_REGNUM:
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h8_set_insts (sd, longval);
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break;
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case TICK_REGNUM:
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case TICK_REGNUM:
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h8_set_ticks (sd, longval);
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cpu->regs[rn] = longval;
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break;
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break;
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}
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}
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return length;
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return length;
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@ -4670,41 +4651,26 @@ h8300_reg_store (SIM_CPU *cpu, int rn, unsigned char *value, int length)
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static int
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static int
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h8300_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int length)
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h8300_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int length)
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{
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{
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SIM_DESC sd = CPU_STATE (cpu);
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int v;
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int v;
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int longreg = 0;
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int longreg = 0;
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init_pointers (sd);
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init_pointers (CPU_STATE (cpu));
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if (!h8300smode && rn >= EXR_REGNUM)
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if (!h8300smode && rn >= EXR_REGNUM)
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rn++;
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rn++;
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switch (rn)
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switch (rn)
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{
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{
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default:
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default:
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sim_io_printf (sd, "sim_fetch_register: bad regnum %d.\n", rn);
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return -1;
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v = 0;
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case PC_REGNUM:
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v = cpu->pc;
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break;
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break;
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case CCR_REGNUM:
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case CCR_REGNUM:
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v = h8_get_ccr (sd);
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break;
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case EXR_REGNUM:
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case EXR_REGNUM:
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v = h8_get_exr (sd);
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break;
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case PC_REGNUM:
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v = h8_get_pc (sd);
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break;
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case SBR_REGNUM:
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case SBR_REGNUM:
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v = h8_get_sbr (sd);
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break;
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case VBR_REGNUM:
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case VBR_REGNUM:
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v = h8_get_vbr (sd);
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break;
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case MACH_REGNUM:
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case MACH_REGNUM:
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v = h8_get_mach (sd);
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break;
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case MACL_REGNUM:
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case MACL_REGNUM:
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v = h8_get_macl (sd);
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break;
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case R0_REGNUM:
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case R0_REGNUM:
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case R1_REGNUM:
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case R1_REGNUM:
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case R2_REGNUM:
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case R2_REGNUM:
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@ -4713,19 +4679,16 @@ h8300_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int length)
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case R5_REGNUM:
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case R5_REGNUM:
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case R6_REGNUM:
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case R6_REGNUM:
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case R7_REGNUM:
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case R7_REGNUM:
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v = h8_get_reg (sd, rn);
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v = cpu->regs[rn];
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break;
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break;
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case CYCLE_REGNUM:
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case CYCLE_REGNUM:
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v = h8_get_cycles (sd);
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longreg = 1;
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break;
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case TICK_REGNUM:
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case TICK_REGNUM:
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v = h8_get_ticks (sd);
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case INST_REGNUM:
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v = cpu->regs[rn];
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longreg = 1;
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longreg = 1;
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break;
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break;
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case INST_REGNUM:
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case ZERO_REGNUM:
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v = h8_get_insts (sd);
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v = 0;
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longreg = 1;
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break;
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break;
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}
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}
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/* In Normal mode PC is 2 byte, but other registers are 4 byte */
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/* In Normal mode PC is 2 byte, but other registers are 4 byte */
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@ -4735,13 +4698,14 @@ h8300_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int length)
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buf[1] = v >> 16;
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buf[1] = v >> 16;
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buf[2] = v >> 8;
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buf[2] = v >> 8;
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buf[3] = v >> 0;
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buf[3] = v >> 0;
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return 4;
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}
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}
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else
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else
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{
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{
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buf[0] = v >> 8;
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buf[0] = v >> 8;
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buf[1] = v;
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buf[1] = v;
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return 2;
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}
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}
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return -1;
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}
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}
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static void
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static void
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