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x86-64: adjust MOVQ to/from SReg attributes

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It is unclear to me why the corresponding MOV (no Q suffix) can be
issued without REX.W, but MOVQ has to have that prefix (bit). Add
NoRex64 and in exchange drop Size64.
This commit is contained in:
Jan Beulich
2022-08-09 09:20:07 +02:00
parent 87bf025228
commit 298d6e70a8
4 changed files with 23 additions and 9 deletions
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17
gas/testsuite/gas/i386/x86-64-segment.l
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@ -5,8 +5,15 @@
5 0002 8C18 mov %ds,\(%rax\) 5 0002 8C18 mov %ds,\(%rax\)
6 0004 8E18 movw \(%rax\),%ds 6 0004 8E18 movw \(%rax\),%ds
7 0006 8E18 mov \(%rax\),%ds 7 0006 8E18 mov \(%rax\),%ds
8 # test segment reg insns with REX 8 # test segment reg insns with avoided REX
9 0008 488CD8 movq %ds,%rax 9 0008 8CD8 mov %ds,%rax
10 000b 488ED8 movq %rax,%ds 10 000a 8CD8 movq %ds,%rax
11 # Force a good alignment. 11 000c 8ED8 mov %rax,%ds
12 000e 0000 .p2align 4,0 12 000e 8ED8 movq %rax,%ds
13 # test segment reg insns with REX
14 0010 418CD8 mov %ds,%r8
15 0013 418CD8 movq %ds,%r8
16 0016 418ED8 mov %r8,%ds
17 0019 418ED8 movq %r8,%ds
18 # Force a good alignment.
19 001c 0+ + *\.p2align 4,0

9
gas/testsuite/gas/i386/x86-64-segment.s
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@ -5,8 +5,15 @@
mov %ds,(%rax) mov %ds,(%rax)
movw (%rax),%ds movw (%rax),%ds
mov (%rax),%ds mov (%rax),%ds
# test segment reg insns with REX # test segment reg insns with avoided REX
mov %ds,%rax
movq %ds,%rax movq %ds,%rax
mov %rax,%ds
movq %rax,%ds movq %rax,%ds
# test segment reg insns with REX
mov %ds,%r8
movq %ds,%r8
mov %r8,%ds
movq %r8,%ds
# Force a good alignment. # Force a good alignment.
.p2align 4,0 .p2align 4,0

2
opcodes/i386-opc.tbl
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@ -148,7 +148,7 @@ movq, 0xb8, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf
// implementation defined value is zero). // implementation defined value is zero).
mov, 0x8c, None, 0, RegMem|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { SReg, Reg16|Reg32|Reg64 } mov, 0x8c, None, 0, RegMem|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { SReg, Reg16|Reg32|Reg64 }
mov, 0x8c, None, 0, D|Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg, Word|Unspecified|BaseIndex } mov, 0x8c, None, 0, D|Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg, Word|Unspecified|BaseIndex }
movq, 0x8c, None, Cpu64, D|RegMem|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg, Reg64 } movq, 0x8c, None, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { SReg, Reg64 }
mov, 0x8e, None, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg16|Reg32|Reg64, SReg } mov, 0x8e, None, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg16|Reg32|Reg64, SReg }
// Move to/from control debug registers. In the 16 or 32bit modes // Move to/from control debug registers. In the 16 or 32bit modes
// they are 32bit. In the 64bit mode they are 64bit. // they are 32bit. In the 64bit mode they are 64bit.

4
opcodes/i386-tbl.h
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@ -323,8 +323,8 @@ const insn_template i386_optab[] =
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } }, 0, 0, 0, 0, 0, 0 } } } },
{ "movq", 0x8c, 2, None, { "movq", 0x8c, 2, None,
{ 1, 0, 0, 1, 0, 0, 0, 3, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,