espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-21 02:24:17 +08:00
Code Issues Packages Projects Releases Wiki Activity

* doc/c-mips.texi (MIPS Opts): Fix typo in last patch.

Browse Source
This commit is contained in:
Jeff Law
2000-02-26 01:48:35 +00:00
parent 36e89602d2
commit 28d33191ee
2 changed files with 5 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
gas/ChangeLog
View File

@ -1,3 +1,7 @@
2000-02-26 Andreas Jaeger <aj@suse.de>
* doc/c-mips.texi (MIPS Opts): Fix typo in last patch.
2000-02-25 Alan Modra <alan@spri.levels.unisa.edu.au> 2000-02-25 Alan Modra <alan@spri.levels.unisa.edu.au>
* config/tc-i386.c (md_assemble): Don't swap intersegment jmp and * config/tc-i386.c (md_assemble): Don't swap intersegment jmp and

2
gas/doc/c-mips.texi
View File

@ -71,7 +71,7 @@ assembly; see @ref{MIPS ISA,, Directives to override the ISA level}.
Assume that 32-bit general purpose registers are available. This Assume that 32-bit general purpose registers are available. This
affects synthetic instructions such as @code{move}, which will assemble affects synthetic instructions such as @code{move}, which will assemble
to a 32-bit or a 64-bit instruction depending on this flag. On some to a 32-bit or a 64-bit instruction depending on this flag. On some
MIPS variants there is be a 32-bit mode flag; when this flag is set, MIPS variants there is a 32-bit mode flag; when this flag is set,
64-bit instructions generate a trap. Also, some 32-bit OSes only save 64-bit instructions generate a trap. Also, some 32-bit OSes only save
the 32-bit registers on a context switch, so it is essential never to the 32-bit registers on a context switch, so it is essential never to
use the 64-bit registers. use the 64-bit registers.