espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-09-19 00:49:47 +08:00
Code Issues Packages Projects Releases Wiki Activity

RISC-V: Mention -mbig-endian and -mlittle-endian in doc

Browse Source 
gas/
    * doc/as.texi: Add -mlittle-endian and -mbig-endian to docs.
    * doc/c-riscv.texi: Likewise.
This commit is contained in:
Marcus Comstedt
2021-01-05 22:50:37 +01:00
committed by Nelson Chu
parent f36ce378b4
commit 286d2f2cd7
3 changed files with 14 additions and 0 deletions

5
gas/ChangeLog

@ -1,3 +1,8 @@
2021-01-06 Marcus Comstedt <marcus@mc.pp.se>
* doc/as.texi: Add -mlittle-endian and -mbig-endian to docs.
* doc/c-riscv.texi: Likewise.
2021-01-06 Marcus Comstedt <marcus@mc.pp.se> 2021-01-06 Marcus Comstedt <marcus@mc.pp.se>
* testsuite/gas/riscv/li32.d: Accept bigriscv in addition * testsuite/gas/riscv/li32.d: Accept bigriscv in addition

1
gas/doc/as.texi

@ -536,6 +536,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
[@b{-fpic}|@b{-fPIC}|@b{-fno-pic}] [@b{-fpic}|@b{-fPIC}|@b{-fno-pic}]
[@b{-march}=@var{ISA}] [@b{-march}=@var{ISA}]
[@b{-mabi}=@var{ABI}] [@b{-mabi}=@var{ABI}]
[@b{-mlittle-endian}|@b{-mbig-endian}]
@end ifset @end ifset
@ifset RL78 @ifset RL78

8
gas/doc/c-riscv.texi

@ -99,6 +99,14 @@ read-only CSR can not be written by the CSR instructions.
@cindex @samp{-mno-csr-check} option, RISC-V @cindex @samp{-mno-csr-check} option, RISC-V
@item -mno-csr-check @item -mno-csr-check
Don't do CSR checking. Don't do CSR checking.
@cindex @samp{-mlittle-endian} option, RISC-V
@item -mlittle-endian
Generate code for a little endian machine.
@cindex @samp{-mbig-endian} option, RISC-V
@item -mbig-endian
Generate code for a big endian machine.
@end table @end table
@c man end @c man end