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S12Z opcodes: Fix bug disassembling certain shift instructions.

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Shift and rotate instructions when the number of bit positions
was an immediate value greater than 1 were incorrectly disassembled.
This change fixes that problem and extends the test to check for
it.

gas/ChangeLog:

  testsuite/gas/s12z/shift.s: Add new test case.
  testsuite/gas/s12z/shift.d: Add expected result.

opcodes/ChangeLog:

  s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case
  if the postbyte matches the appropriate pattern.
This commit is contained in:
John Darrington
2018-11-20 18:50:30 +01:00
parent 51534d7ab8
commit 27f42a4ddb
5 changed files with 40 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2018-11-21 John Darrington <john@darrington.wattle.id.au>
* testsuite/gas/s12z/shift.s: Add new test case.
* testsuite/gas/s12z/shift.d: Add expected result.
2018-11-21 John Darrington <john@darrington.wattle.id.au> 2018-11-21 John Darrington <john@darrington.wattle.id.au>
* config/tc-s12z.c (opcodes): bhs, blo: New members. * config/tc-s12z.c (opcodes): bhs, blo: New members.

4
gas/testsuite/gas/s12z/shift.d
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@ -1,5 +1,5 @@
#objdump: -d #objdump: -d
#name: #name: Tests for shift and rotate instructions
#source: shift.s #source: shift.s
@ -20,3 +20,5 @@ Disassembly of section .text:
17: 10 3e 8e lsr.p \(d6,x\), #2 17: 10 3e 8e lsr.p \(d6,x\), #2
1a: 10 f4 bf asl d7, #1 1a: 10 f4 bf asl d7, #1
1d: 10 bc bd asr d1, #2 1d: 10 bc bd asr d1, #2
20: 16 de 78 asl d6, d6, #17
23: 16 d6 78 asl d6, d6, #16

2
gas/testsuite/gas/s12z/shift.s
View File

@ -9,3 +9,5 @@
lsr.p (d6,x), #2 lsr.p (d6,x), #2
asl d7, #1 asl d7, #1
asr d1, #2 asr d1, #2
asl d6, d6, #17
asl d6, d6, #16

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2018-11-21 John Darrington <john@darrington.wattle.id.au>
* s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case
if the postbyte matches the appropriate pattern.
2018-11-13 Francois H. Theron <francois.theron@netronome.com> 2018-11-13 Francois H. Theron <francois.theron@netronome.com>
* nfp-dis.c: Fix crc[] disassembly if operands are swapped. * nfp-dis.c: Fix crc[] disassembly if operands are swapped.

12
opcodes/s12z-dis.c
View File

@ -2363,13 +2363,18 @@ print_insn_shift (bfd_vma memaddr, struct disassemble_info* info, uint8_t byte)
break; break;
case SB_REG_REG_N: case SB_REG_REG_N:
if (sb & 0x08) {
uint8_t xb;
read_memory (memaddr + 1, &xb, 1, info);
/* This case is slightly unusual.
If XB matches the binary pattern 0111XXXX, then instead of
interpreting this as a general OPR postbyte in the IMMe4 mode,
the XB byte is interpreted in s special way. */
if ((xb & 0xF0) == 0x70)
{ {
operand_separator (info); operand_separator (info);
if (byte & 0x10) if (byte & 0x10)
{ {
uint8_t xb;
read_memory (memaddr + 1, &xb, 1, info);
int shift = ((sb & 0x08) >> 3) | ((xb & 0x0f) << 1); int shift = ((sb & 0x08) >> 3) | ((xb & 0x0f) << 1);
(*info->fprintf_func) (info->stream, "#%d", shift); (*info->fprintf_func) (info->stream, "#%d", shift);
} }
@ -2382,6 +2387,7 @@ print_insn_shift (bfd_vma memaddr, struct disassemble_info* info, uint8_t byte)
{ {
opr_decode (memaddr + 1, info); opr_decode (memaddr + 1, info);
} }
}
break; break;
case SB_REG_OPR_OPR: case SB_REG_OPR_OPR:
{ {