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RISC-V: Add T-Head MemIdx vendor extension
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMemIdx extension, a collection of T-Head specific
GPR memory access instructions.
The 'th' prefix and the "XTheadMemIdx" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
In total XTheadCmo introduces the following 44 instructions
(BU,HU,WU only for loads (zero-extend instead of sign-extend)):
* {L,S}{D,W,WU,H,HU,B,BU}{IA,IB} rd, rs1, imm5, imm2
* {L,S}R{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2
* {L,S}UR{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This commit is contained in:
Christoph Müllner
committed by
Philipp Tomsich
Philipp Tomsich
parent
f511f80fa3
commit
27cfd142d0
@ -2216,6 +2216,95 @@
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#define MASK_TH_MULSH 0xfe00707f
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#define MATCH_TH_MULSW 0x2600100b
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#define MASK_TH_MULSW 0xfe00707f
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/* Vendor-specific (T-Head) XTheadMemIdx instructions. */
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#define MATCH_TH_LDIA 0x7800400b
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#define MASK_TH_LDIA 0xf800707f
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#define MATCH_TH_LDIB 0x6800400b
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#define MASK_TH_LDIB 0xf800707f
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#define MATCH_TH_LWIA 0x5800400b
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#define MASK_TH_LWIA 0xf800707f
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#define MATCH_TH_LWIB 0x4800400b
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#define MASK_TH_LWIB 0xf800707f
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#define MATCH_TH_LWUIA 0xd800400b
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#define MASK_TH_LWUIA 0xf800707f
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#define MATCH_TH_LWUIB 0xc800400b
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#define MASK_TH_LWUIB 0xf800707f
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#define MATCH_TH_LHIA 0x3800400b
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#define MASK_TH_LHIA 0xf800707f
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#define MATCH_TH_LHIB 0x2800400b
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#define MASK_TH_LHIB 0xf800707f
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#define MATCH_TH_LHUIA 0xb800400b
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#define MASK_TH_LHUIA 0xf800707f
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#define MATCH_TH_LHUIB 0xa800400b
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#define MASK_TH_LHUIB 0xf800707f
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#define MATCH_TH_LBIA 0x1800400b
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#define MASK_TH_LBIA 0xf800707f
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#define MATCH_TH_LBIB 0x0800400b
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#define MASK_TH_LBIB 0xf800707f
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#define MATCH_TH_LBUIA 0x9800400b
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#define MASK_TH_LBUIA 0xf800707f
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#define MATCH_TH_LBUIB 0x8800400b
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#define MASK_TH_LBUIB 0xf800707f
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#define MATCH_TH_SDIA 0x7800500b
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#define MASK_TH_SDIA 0xf800707f
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#define MATCH_TH_SDIB 0x6800500b
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#define MASK_TH_SDIB 0xf800707f
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#define MATCH_TH_SWIA 0x5800500b
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#define MASK_TH_SWIA 0xf800707f
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#define MATCH_TH_SWIB 0x4800500b
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#define MASK_TH_SWIB 0xf800707f
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#define MATCH_TH_SHIA 0x3800500b
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#define MASK_TH_SHIA 0xf800707f
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#define MATCH_TH_SHIB 0x2800500b
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#define MASK_TH_SHIB 0xf800707f
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#define MATCH_TH_SBIA 0x1800500b
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#define MASK_TH_SBIA 0xf800707f
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#define MATCH_TH_SBIB 0x0800500b
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#define MASK_TH_SBIB 0xf800707f
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#define MATCH_TH_LRD 0x6000400b
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#define MASK_TH_LRD 0xf800707f
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#define MATCH_TH_LRW 0x4000400b
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#define MASK_TH_LRW 0xf800707f
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#define MATCH_TH_LRWU 0xc000400b
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#define MASK_TH_LRWU 0xf800707f
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#define MATCH_TH_LRH 0x2000400b
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#define MASK_TH_LRH 0xf800707f
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#define MATCH_TH_LRHU 0xa000400b
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#define MASK_TH_LRHU 0xf800707f
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#define MATCH_TH_LRB 0x0000400b
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#define MASK_TH_LRB 0xf800707f
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#define MATCH_TH_LRBU 0x8000400b
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#define MASK_TH_LRBU 0xf800707f
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#define MATCH_TH_SRD 0x6000500b
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#define MASK_TH_SRD 0xf800707f
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#define MATCH_TH_SRW 0x4000500b
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#define MASK_TH_SRW 0xf800707f
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#define MATCH_TH_SRH 0x2000500b
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#define MASK_TH_SRH 0xf800707f
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#define MATCH_TH_SRB 0x0000500b
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#define MASK_TH_SRB 0xf800707f
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#define MATCH_TH_LURD 0x7000400b
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#define MASK_TH_LURD 0xf800707f
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#define MATCH_TH_LURW 0x5000400b
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#define MASK_TH_LURW 0xf800707f
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#define MATCH_TH_LURWU 0xd000400b
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#define MASK_TH_LURWU 0xf800707f
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#define MATCH_TH_LURH 0x3000400b
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#define MASK_TH_LURH 0xf800707f
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#define MATCH_TH_LURHU 0xb000400b
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#define MASK_TH_LURHU 0xf800707f
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#define MATCH_TH_LURB 0x1000400b
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#define MASK_TH_LURB 0xf800707f
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#define MATCH_TH_LURBU 0x9000400b
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#define MASK_TH_LURBU 0xf800707f
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#define MATCH_TH_SURD 0x7000500b
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#define MASK_TH_SURD 0xf800707f
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#define MATCH_TH_SURW 0x5000500b
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#define MASK_TH_SURW 0xf800707f
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#define MATCH_TH_SURH 0x3000500b
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#define MASK_TH_SURH 0xf800707f
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#define MATCH_TH_SURB 0x1000500b
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#define MASK_TH_SURB 0xf800707f
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/* Vendor-specific (T-Head) XTheadSync instructions. */
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#define MATCH_TH_SFENCE_VMAS 0x0400000b
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#define MASK_TH_SFENCE_VMAS 0xfe007fff
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@ -3021,6 +3110,51 @@ DECLARE_INSN(th_mulaw, MATCH_TH_MULAW, MASK_TH_MULAW)
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DECLARE_INSN(th_muls, MATCH_TH_MULS, MASK_TH_MULS)
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DECLARE_INSN(th_mulsh, MATCH_TH_MULSH, MASK_TH_MULSH)
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DECLARE_INSN(th_mulsw, MATCH_TH_MULSW, MASK_TH_MULSW)
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/* Vendor-specific (T-Head) XTheadMemIdx instructions. */
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DECLARE_INSN(th_ldia, MATCH_TH_LDIA, MASK_TH_LDIA)
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DECLARE_INSN(th_ldib, MATCH_TH_LDIB, MASK_TH_LDIB)
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DECLARE_INSN(th_lwia, MATCH_TH_LWIA, MASK_TH_LWIA)
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DECLARE_INSN(th_lwib, MATCH_TH_LWIB, MASK_TH_LWIB)
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DECLARE_INSN(th_lwuia, MATCH_TH_LWUIA, MASK_TH_LWUIA)
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DECLARE_INSN(th_lwuib, MATCH_TH_LWUIB, MASK_TH_LWUIB)
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DECLARE_INSN(th_lhia, MATCH_TH_LHIA, MASK_TH_LHIA)
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DECLARE_INSN(th_lhib, MATCH_TH_LHIB, MASK_TH_LHIB)
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DECLARE_INSN(th_lhuia, MATCH_TH_LHUIA, MASK_TH_LHUIA)
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DECLARE_INSN(th_lhuib, MATCH_TH_LHUIB, MASK_TH_LHUIB)
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DECLARE_INSN(th_lbia, MATCH_TH_LBIA, MASK_TH_LBIA)
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DECLARE_INSN(th_lbib, MATCH_TH_LBIB, MASK_TH_LBIB)
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DECLARE_INSN(th_lbuia, MATCH_TH_LBUIA, MASK_TH_LBUIA)
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DECLARE_INSN(th_lbuib, MATCH_TH_LBUIB, MASK_TH_LBUIB)
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DECLARE_INSN(th_sdia, MATCH_TH_SDIA, MASK_TH_SDIA)
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DECLARE_INSN(th_sdib, MATCH_TH_SDIB, MASK_TH_SDIB)
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DECLARE_INSN(th_swia, MATCH_TH_SWIA, MASK_TH_SWIA)
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DECLARE_INSN(th_swib, MATCH_TH_SWIB, MASK_TH_SWIB)
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DECLARE_INSN(th_shia, MATCH_TH_SHIA, MASK_TH_SHIA)
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DECLARE_INSN(th_shib, MATCH_TH_SHIB, MASK_TH_SHIB)
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DECLARE_INSN(th_sbia, MATCH_TH_SBIA, MASK_TH_SBIA)
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DECLARE_INSN(th_sbib, MATCH_TH_SBIB, MASK_TH_SBIB)
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DECLARE_INSN(th_lrd, MATCH_TH_LRD, MASK_TH_LRD)
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DECLARE_INSN(th_lrw, MATCH_TH_LRW, MASK_TH_LRW)
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DECLARE_INSN(th_lrwu, MATCH_TH_LRWU, MASK_TH_LRWU)
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DECLARE_INSN(th_lrh, MATCH_TH_LRH, MASK_TH_LRH)
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DECLARE_INSN(th_lrhu, MATCH_TH_LRHU, MASK_TH_LRHU)
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DECLARE_INSN(th_lrb, MATCH_TH_LRB, MASK_TH_LRB)
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DECLARE_INSN(th_lrbu, MATCH_TH_LRBU, MASK_TH_LRBU)
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DECLARE_INSN(th_srd, MATCH_TH_SRD, MASK_TH_SRD)
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DECLARE_INSN(th_srw, MATCH_TH_SRW, MASK_TH_SRW)
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DECLARE_INSN(th_srh, MATCH_TH_SRH, MASK_TH_SRH)
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DECLARE_INSN(th_srb, MATCH_TH_SRB, MASK_TH_SRB)
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DECLARE_INSN(th_lurd, MATCH_TH_LURD, MASK_TH_LURD)
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DECLARE_INSN(th_lurw, MATCH_TH_LURW, MASK_TH_LURW)
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DECLARE_INSN(th_lurwu, MATCH_TH_LURWU, MASK_TH_LURWU)
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DECLARE_INSN(th_lurh, MATCH_TH_LURH, MASK_TH_LURH)
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DECLARE_INSN(th_lurhu, MATCH_TH_LURHU, MASK_TH_LURHU)
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DECLARE_INSN(th_lurb, MATCH_TH_LURB, MASK_TH_LURB)
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DECLARE_INSN(th_lurbu, MATCH_TH_LURBU, MASK_TH_LURBU)
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DECLARE_INSN(th_surd, MATCH_TH_SURD, MASK_TH_SURD)
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DECLARE_INSN(th_surw, MATCH_TH_SURW, MASK_TH_SURW)
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DECLARE_INSN(th_surh, MATCH_TH_SURH, MASK_TH_SURH)
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DECLARE_INSN(th_surb, MATCH_TH_SURB, MASK_TH_SURB)
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/* Vendor-specific (T-Head) XTheadSync instructions. */
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DECLARE_INSN(th_sfence_vmas, MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS)
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DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC)
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@ -422,6 +422,7 @@ enum riscv_insn_class
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INSN_CLASS_XTHEADCONDMOV,
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INSN_CLASS_XTHEADFMEMIDX,
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INSN_CLASS_XTHEADMAC,
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INSN_CLASS_XTHEADMEMIDX,
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INSN_CLASS_XTHEADSYNC,
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};
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