mirror of
https://github.com/espressif/binutils-gdb.git
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include/opcode/
* mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31) (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH) (MIPS16_INSN_COND_BRANCH): Delete. opcodes/ * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags. (WR_SP): Replace with... (MOD_SP): ...this. (mips16_opcodes): Update accordingly. * mips-dis.c (print_insn_mips16): Likewise. gas/ * config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same flags for MIPS16 and non-MIPS16 instructions. (gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block. (gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too. (gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling. (can_swap_branch_p, get_append_method): Use the same flags for MIPS16 and non-MIPS16 instructions. Fix formatting.
This commit is contained in:
Richard Sandiford
@ -1,3 +1,13 @@
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2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same
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flags for MIPS16 and non-MIPS16 instructions.
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(gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block.
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(gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too.
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(gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling.
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(can_swap_branch_p, get_append_method): Use the same flags for MIPS16
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and non-MIPS16 instructions. Fix formatting.
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2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (reg_needs_delay): Move later in file.
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@ -3547,10 +3547,6 @@ delayed_branch_p (const struct mips_cl_insn *ip)
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static inline bfd_boolean
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compact_branch_p (const struct mips_cl_insn *ip)
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{
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if (mips_opts.mips16)
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return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
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| MIPS16_INSN_COND_BRANCH)) != 0;
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else
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return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
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| INSN2_COND_BRANCH)) != 0;
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}
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@ -3561,9 +3557,7 @@ static inline bfd_boolean
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uncond_branch_p (const struct mips_cl_insn *ip)
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{
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return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
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|| (mips_opts.mips16
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? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
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: (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
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|| (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
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}
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/* Return true if IP is a branch-likely instruction. */
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@ -3602,9 +3596,9 @@ gpr_mod_mask (const struct mips_cl_insn *ip)
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mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
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if (pinfo2 & INSN2_MOD_GPR_MF)
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mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
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}
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if (pinfo2 & INSN2_MOD_SP)
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mask |= 1 << SP;
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}
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return mask;
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}
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@ -3629,8 +3623,6 @@ gpr_read_mask (const struct mips_cl_insn *ip)
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mask |= 1 << TREG;
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if (pinfo & MIPS16_INSN_READ_SP)
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mask |= 1 << SP;
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if (pinfo & MIPS16_INSN_READ_31)
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mask |= 1 << RA;
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if (pinfo & MIPS16_INSN_READ_Z)
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mask |= 1 << (mips16_to_32_reg_map
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[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
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@ -3647,11 +3639,11 @@ gpr_read_mask (const struct mips_cl_insn *ip)
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mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
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if (pinfo2 & INSN2_READ_GP)
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mask |= 1 << GP;
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if (pinfo2 & INSN2_READ_GPR_31)
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mask |= 1 << RA;
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if (pinfo2 & INSN2_READ_GPR_Z)
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mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
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}
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if (pinfo2 & INSN2_READ_GPR_31)
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mask |= 1 << RA;
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if (mips_opts.micromips)
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{
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if (pinfo2 & INSN2_READ_GPR_MC)
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@ -3697,8 +3689,6 @@ gpr_write_mask (const struct mips_cl_insn *ip)
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mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
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if (pinfo & MIPS16_INSN_WRITE_T)
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mask |= 1 << TREG;
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if (pinfo & MIPS16_INSN_WRITE_SP)
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mask |= 1 << SP;
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if (pinfo & MIPS16_INSN_WRITE_31)
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mask |= 1 << RA;
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if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
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@ -5705,9 +5695,7 @@ can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
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/* If the previous instruction uses the PC, we can not swap. */
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prev_pinfo2 = history[0].insn_mo->pinfo2;
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if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
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return FALSE;
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if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
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if (prev_pinfo2 & INSN2_READ_PC)
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return FALSE;
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/* If the previous instruction has an incorrect size for a fixed
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@ -5781,7 +5769,7 @@ static enum append_method
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get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
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bfd_reloc_code_real_type *reloc_type)
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{
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unsigned long pinfo;
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unsigned long pinfo, pinfo2;
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/* The relaxed version of a macro sequence must be inherently
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hazard-free. */
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@ -5800,9 +5788,11 @@ get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
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return APPEND_SWAP;
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pinfo = ip->insn_mo->pinfo;
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pinfo2 = ip->insn_mo->pinfo2;
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if (mips_opts.mips16
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&& ISA_SUPPORTS_MIPS16E
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&& (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
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&& ((pinfo & MIPS16_INSN_READ_X) != 0
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|| (pinfo2 & INSN2_READ_GPR_31) != 0))
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return APPEND_ADD_COMPACT;
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return APPEND_ADD_WITH_NOP;
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@ -1,3 +1,9 @@
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2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
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* mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
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(MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
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(MIPS16_INSN_COND_BRANCH): Delete.
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2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
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Kirill Yukhin <kirill.yukhin@intel.com>
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Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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@ -1644,8 +1644,6 @@ extern int bfd_mips_num_opcodes;
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#define MIPS16_INSN_WRITE_Z 0x00000004
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/* Modifies the T ($24) register. */
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#define MIPS16_INSN_WRITE_T 0x00000008
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/* Modifies the SP ($29) register. */
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#define MIPS16_INSN_WRITE_SP 0x00000010
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/* Modifies the RA ($31) register. */
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#define MIPS16_INSN_WRITE_31 0x00000020
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/* Modifies the general purpose register in MIPS16OP_*_REG32R. */
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@ -1660,16 +1658,8 @@ extern int bfd_mips_num_opcodes;
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#define MIPS16_INSN_READ_T 0x00000400
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/* Reads the SP ($29) register. */
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#define MIPS16_INSN_READ_SP 0x00000800
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/* Reads the RA ($31) register. */
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#define MIPS16_INSN_READ_31 0x00001000
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/* Reads the program counter. */
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#define MIPS16_INSN_READ_PC 0x00002000
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/* Reads the general purpose register in MIPS16OP_*_REGR32. */
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#define MIPS16_INSN_READ_GPR_X 0x00004000
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/* Is an unconditional branch insn. */
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#define MIPS16_INSN_UNCOND_BRANCH 0x00008000
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/* Is a conditional branch insn. */
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#define MIPS16_INSN_COND_BRANCH 0x00010000
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/* The following flags have the same value for the mips16 opcode
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table:
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@ -1,3 +1,11 @@
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2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
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* mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
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(WR_SP): Replace with...
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(MOD_SP): ...this.
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(mips16_opcodes): Update accordingly.
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* mips-dis.c (print_insn_mips16): Likewise.
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2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
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* mips16-opc.c (mips16_opcodes): Reformat.
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@ -1749,15 +1749,15 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
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/* Figure out branch instruction type and delay slot information. */
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if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
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info->branch_delay_insns = 1;
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if ((op->pinfo & (INSN_UNCOND_BRANCH_DELAY
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| MIPS16_INSN_UNCOND_BRANCH)) != 0)
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if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
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|| (op->pinfo2 & INSN2_UNCOND_BRANCH) != 0)
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{
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if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
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info->insn_type = dis_jsr;
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else
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info->insn_type = dis_branch;
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}
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else if ((op->pinfo & MIPS16_INSN_COND_BRANCH) != 0)
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else if ((op->pinfo2 & INSN2_COND_BRANCH) != 0)
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info->insn_type = dis_condbranch;
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return length;
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@ -143,14 +143,11 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
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the opcodes table. */
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#define UBD INSN_UNCOND_BRANCH_DELAY
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#define UBR MIPS16_INSN_UNCOND_BRANCH
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#define CBR MIPS16_INSN_COND_BRANCH
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#define WR_x MIPS16_INSN_WRITE_X
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#define WR_y MIPS16_INSN_WRITE_Y
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#define WR_z MIPS16_INSN_WRITE_Z
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#define WR_T MIPS16_INSN_WRITE_T
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#define WR_SP MIPS16_INSN_WRITE_SP
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#define WR_31 MIPS16_INSN_WRITE_31
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#define WR_Y MIPS16_INSN_WRITE_GPR_Y
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@ -159,8 +156,6 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
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#define RD_Z MIPS16_INSN_READ_Z
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#define RD_T MIPS16_INSN_READ_T
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#define RD_SP MIPS16_INSN_READ_SP
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#define RD_31 MIPS16_INSN_READ_31
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#define RD_PC MIPS16_INSN_READ_PC
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#define RD_X MIPS16_INSN_READ_GPR_X
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#define WR_HI INSN_WRITE_HI
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@ -171,6 +166,12 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
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#define NODS INSN_NO_DELAY_SLOT
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#define TRAP INSN_NO_DELAY_SLOT
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#define MOD_SP INSN2_MOD_SP
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#define RD_31 INSN2_READ_GPR_31
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#define RD_PC INSN2_READ_PC
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#define UBR INSN2_UNCOND_BRANCH
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#define CBR INSN2_COND_BRANCH
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#define I1 INSN_ISA1
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#define I3 INSN_ISA3
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#define I32 INSN_ISA32
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@ -181,26 +182,26 @@ const struct mips_opcode mips16_opcodes[] =
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{
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/* name, args, match, mask, pinfo, pinfo2, membership */
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{"nop", "", 0x6500, 0xffff, RD_Z, 0, I1, 0, 0 }, /* move $0,$Z */
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{"la", "x,A", 0x0800, 0xf800, WR_x|RD_PC, 0, I1, 0, 0 },
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{"la", "x,A", 0x0800, 0xf800, WR_x, RD_PC, I1, 0, 0 },
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{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 },
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{"addiu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, I1, 0, 0 },
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{"addiu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, I1, 0, 0 },
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{"addiu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1, 0, 0 },
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{"addiu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1, 0, 0 },
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{"addiu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, I1, 0, 0 },
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{"addiu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
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{"addiu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
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{"addiu", "x,P,V", 0x0800, 0xf800, WR_x, RD_PC, I1, 0, 0 },
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{"addiu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, I1, 0, 0 },
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{"addu", "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y, 0, I1, 0, 0 },
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{"addu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, I1, 0, 0 },
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{"addu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, I1, 0, 0 },
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{"addu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1, 0, 0 },
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{"addu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1, 0, 0 },
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{"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, I1, 0, 0 },
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{"addu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
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{"addu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
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{"addu", "x,P,V", 0x0800, 0xf800, WR_x, RD_PC, I1, 0, 0 },
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{"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, I1, 0, 0 },
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{"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0, I1, 0, 0 },
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{"b", "q", 0x1000, 0xf800, UBR, 0, I1, 0, 0 },
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{"b", "q", 0x1000, 0xf800, 0, UBR, I1, 0, 0 },
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{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1, 0, 0 },
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{"beq", "x,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 },
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{"beqz", "x,p", 0x2000, 0xf800, CBR|RD_x, 0, I1, 0, 0 },
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{"beqz", "x,p", 0x2000, 0xf800, RD_x, CBR, I1, 0, 0 },
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{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 },
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{"bge", "x,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 },
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{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 },
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@ -219,26 +220,26 @@ const struct mips_opcode mips16_opcodes[] =
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{"bltu", "x,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 },
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{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1, 0, 0 },
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{"bne", "x,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 },
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{"bnez", "x,p", 0x2800, 0xf800, CBR|RD_x, 0, I1, 0, 0 },
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{"bnez", "x,p", 0x2800, 0xf800, RD_x, CBR, I1, 0, 0 },
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{"break", "6", 0xe805, 0xf81f, TRAP, 0, I1, 0, 0 },
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{"bteqz", "p", 0x6000, 0xff00, CBR|RD_T, 0, I1, 0, 0 },
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{"btnez", "p", 0x6100, 0xff00, CBR|RD_T, 0, I1, 0, 0 },
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{"bteqz", "p", 0x6000, 0xff00, RD_T, CBR, I1, 0, 0 },
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{"btnez", "p", 0x6100, 0xff00, RD_T, CBR, I1, 0, 0 },
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{"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1, 0, 0 },
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{"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0, I1, 0, 0 },
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{"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1, 0, 0 },
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{"dla", "y,E", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3, 0, 0 },
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{"dla", "y,E", 0xfe00, 0xff00, WR_y, RD_PC, I3, 0, 0 },
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{"daddiu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3, 0, 0 },
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{"daddiu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3, 0, 0 },
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{"daddiu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3, 0, 0 },
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{"daddiu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3, 0, 0 },
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{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3, 0, 0 },
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{"daddiu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
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{"daddiu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
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{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_y, RD_PC, I3, 0, 0 },
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{"daddiu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3, 0, 0 },
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{"daddu", "z,v,y", 0xe000, 0xf803, WR_z|RD_x|RD_y, 0, I3, 0, 0 },
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{"daddu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3, 0, 0 },
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{"daddu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3, 0, 0 },
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{"daddu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3, 0, 0 },
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{"daddu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3, 0, 0 },
|
||||
{"daddu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3, 0, 0 },
|
||||
{"daddu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
|
||||
{"daddu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
|
||||
{"daddu", "y,P,W", 0xfe00, 0xff00, WR_y, RD_PC, I3, 0, 0 },
|
||||
{"daddu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3, 0, 0 },
|
||||
{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 },
|
||||
{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I1, 0, 0 },
|
||||
@ -281,28 +282,28 @@ const struct mips_opcode mips16_opcodes[] =
|
||||
{"jal", "a", 0x1800, 0xfc00, UBD|WR_31, 0, I1, 0, 0 },
|
||||
{"jalx", "i", 0x1c00, 0xfc00, UBD|WR_31, 0, I1, 0, 0 },
|
||||
{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1, 0, 0 },
|
||||
{"jr", "R", 0xe820, 0xffff, UBD|RD_31, 0, I1, 0, 0 },
|
||||
{"jr", "R", 0xe820, 0xffff, UBD, RD_31, I1, 0, 0 },
|
||||
{"j", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1, 0, 0 },
|
||||
{"j", "R", 0xe820, 0xffff, UBD|RD_31, 0, I1, 0, 0 },
|
||||
{"j", "R", 0xe820, 0xffff, UBD, RD_31, I1, 0, 0 },
|
||||
/* MIPS16e compact branches. We keep them near the ordinary branches
|
||||
so that we easily find them when converting a normal branch to a
|
||||
compact one. */
|
||||
{"jalrc", "x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|NODS, 0, I32, 0, 0 },
|
||||
{"jalrc", "R,x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|NODS, 0, I32, 0, 0 },
|
||||
{"jrc", "x", 0xe880, 0xf8ff, UBR|RD_x|NODS, 0, I32, 0, 0 },
|
||||
{"jrc", "R", 0xe8a0, 0xffff, UBR|RD_31|NODS, 0, I32, 0, 0 },
|
||||
{"jalrc", "x", 0xe8c0, 0xf8ff, WR_31|RD_x|NODS, UBR, I32, 0, 0 },
|
||||
{"jalrc", "R,x", 0xe8c0, 0xf8ff, WR_31|RD_x|NODS, UBR, I32, 0, 0 },
|
||||
{"jrc", "x", 0xe880, 0xf8ff, RD_x|NODS, UBR, I32, 0, 0 },
|
||||
{"jrc", "R", 0xe8a0, 0xffff, NODS, UBR|RD_31, I32, 0, 0 },
|
||||
{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0, I1, 0, 0 },
|
||||
{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0, I1, 0, 0 },
|
||||
{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, 0, I3, 0, 0 },
|
||||
{"ld", "y,B", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3, 0, 0 },
|
||||
{"ld", "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3, 0, 0 },
|
||||
{"ld", "y,B", 0xfc00, 0xff00, WR_y, RD_PC, I3, 0, 0 },
|
||||
{"ld", "y,D(P)", 0xfc00, 0xff00, WR_y, RD_PC, I3, 0, 0 },
|
||||
{"ld", "y,D(S)", 0xf800, 0xff00, WR_y|RD_SP, 0, I3, 0, 0 },
|
||||
{"lh", "y,H(x)", 0x8800, 0xf800, WR_y|RD_x, 0, I1, 0, 0 },
|
||||
{"lhu", "y,H(x)", 0xa800, 0xf800, WR_y|RD_x, 0, I1, 0, 0 },
|
||||
{"li", "x,U", 0x6800, 0xf800, WR_x, 0, I1, 0, 0 },
|
||||
{"lw", "y,W(x)", 0x9800, 0xf800, WR_y|RD_x, 0, I1, 0, 0 },
|
||||
{"lw", "x,A", 0xb000, 0xf800, WR_x|RD_PC, 0, I1, 0, 0 },
|
||||
{"lw", "x,V(P)", 0xb000, 0xf800, WR_x|RD_PC, 0, I1, 0, 0 },
|
||||
{"lw", "x,A", 0xb000, 0xf800, WR_x, RD_PC, I1, 0, 0 },
|
||||
{"lw", "x,V(P)", 0xb000, 0xf800, WR_x, RD_PC, I1, 0, 0 },
|
||||
{"lw", "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP, 0, I1, 0, 0 },
|
||||
{"lwu", "y,W(x)", 0xb800, 0xf800, WR_y|RD_x, 0, I3, 0, 0 },
|
||||
{"mfhi", "x", 0xe810, 0xf8ff, WR_x|RD_HI, 0, I1, 0, 0 },
|
||||
@ -321,8 +322,8 @@ const struct mips_opcode mips16_opcodes[] =
|
||||
{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"sb", "y,5(x)", 0xc000, 0xf800, RD_y|RD_x, 0, I1, 0, 0 },
|
||||
{"sd", "y,D(x)", 0x7800, 0xf800, RD_y|RD_x, 0, I3, 0, 0 },
|
||||
{"sd", "y,D(S)", 0xf900, 0xff00, RD_y|RD_PC, 0, I3, 0, 0 },
|
||||
{"sd", "R,C(S)", 0xfa00, 0xff00, RD_31|RD_PC, 0, I1, 0, 0 },
|
||||
{"sd", "y,D(S)", 0xf900, 0xff00, RD_y, RD_PC, I3, 0, 0 },
|
||||
{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_PC|RD_31, I1, 0, 0 },
|
||||
{"sh", "y,H(x)", 0xc800, 0xf800, RD_y|RD_x, 0, I1, 0, 0 },
|
||||
{"sllv", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 },
|
||||
{"sll", "x,w,<", 0x3000, 0xf803, WR_x|RD_y, 0, I1, 0, 0 },
|
||||
@ -344,11 +345,11 @@ const struct mips_opcode mips16_opcodes[] =
|
||||
{"subu", "x,I", 0, (int) M_SUBU_I_2, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0, I1, 0, 0 },
|
||||
{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0, I1, 0, 0 },
|
||||
{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0, I1, 0, 0 },
|
||||
{"sw", "R,V(S)", 0x6200, 0xff00, RD_SP, RD_31, I1, 0, 0 },
|
||||
{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, I1, 0, 0 },
|
||||
/* MIPS16e additions */
|
||||
{"restore", "M", 0x6400, 0xff80, WR_31|RD_SP|WR_SP|NODS, 0, I32, 0, 0 },
|
||||
{"save", "m", 0x6480, 0xff80, RD_31|RD_SP|WR_SP|NODS, 0, I32, 0, 0 },
|
||||
{"restore", "M", 0x6400, 0xff80, WR_31|NODS, MOD_SP, I32, 0, 0 },
|
||||
{"save", "m", 0x6480, 0xff80, NODS, MOD_SP|RD_31, I32, 0, 0 },
|
||||
{"sdbbp", "6", 0xe801, 0xf81f, TRAP, 0, I32, 0, 0 },
|
||||
{"seb", "x", 0xe891, 0xf8ff, WR_x|RD_x, 0, I32, 0, 0 },
|
||||
{"seh", "x", 0xe8b1, 0xf8ff, WR_x|RD_x, 0, I32, 0, 0 },
|
||||
|
||||
Reference in New Issue
Block a user