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Removes support in the ARM assembler for the unsigned variants of the VQ(R)DMLAH and VQ(R)DMLASH MVE instructions.

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Previously GAS would accept .u32, .u16 and .u8 suffixes to the VQ(R)DMLAH and VQ(R)DMLASH
instructions, however the Armv8.1-M Mainline specification states that these functions only
have signed variations (.s32, .s16 and .s8 suffixes).
This is documented here:
https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf?_ga=2.143079093.1892401233.1563295591-999473562.1560847439#page=1183

gas	* config/tc-arm.c (do_mve_vqdmlah): Use N_S_32 macro.
	(do_neon_qrdmlah): Use N_S_32 macro.
	* testsuite/gas/arm/mve-vqdmlah-bad.d: New test.
	* testsuite/gas/arm/mve-vqdmlah-bad.l: New test.
	* testsuite/gas/arm/mve-vqdmlah-bad.s: New test.
	* testsuite/gas/arm/mve-vqdmlah.d: Remove unsigned instruction tests.
	* testsuite/gas/arm/mve-vqdmlah.s: Remove unsigned instruction tests.
	* testsuite/gas/arm/mve-vqdmlash-bad.d: New test.
	* testsuite/gas/arm/mve-vqdmlash-bad.l: New test.
	* testsuite/gas/arm/mve-vqdmlash-bad.s: New test.
	* testsuite/gas/arm/mve-vqdmlash.d: Remove unsigned instruction tests.
	* testsuite/gas/arm/mve-vqdmlash.s: Remove unsigned instruction tests.

opcodes	* arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
	instructions.
This commit is contained in:
Barnaby Wilks
2019-08-05 12:43:38 +01:00
committed by Nick Clifton
parent a80cf5d88e
commit 23d188c74e
14 changed files with 64 additions and 2716 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
* arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
instructions.
2019-07-30 Mel Chen <mel.chen@sifive.com>
* riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,

8
opcodes/arm-dis.c
View File

@ -3019,25 +3019,25 @@ static const struct mopcode32 mve_opcodes[] =
/* Vector VQDMLAH. */
{ARM_FEATURE_COPROC (FPU_MVE),
MVE_VQDMLAH,
0xee000e60, 0xef811f70,
0xee000e60, 0xff811f70,
"vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VQRDMLAH. */
{ARM_FEATURE_COPROC (FPU_MVE),
MVE_VQRDMLAH,
0xee000e40, 0xef811f70,
0xee000e40, 0xff811f70,
"vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VQDMLASH. */
{ARM_FEATURE_COPROC (FPU_MVE),
MVE_VQDMLASH,
0xee001e60, 0xef811f70,
0xee001e60, 0xff811f70,
"vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VQRDMLASH. */
{ARM_FEATURE_COPROC (FPU_MVE),
MVE_VQRDMLASH,
0xee001e40, 0xef811f70,
0xee001e40, 0xff811f70,
"vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VQDMLSDH. */