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Add support for Score target.
This commit is contained in:
Nick Clifton
282
include/opcode/score-datadep.h
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282
include/opcode/score-datadep.h
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/* score-datadep.h -- Score Instructions data dependency table
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Copyright 2006 Free Software Foundation, Inc.
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Contributed by:
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Mei Ligang (ligang@sunnorth.com.cn)
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Pei-Lin Tsai (pltsai@sunplus.com)
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
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Boston, MA 02110-1301, USA. */
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#ifndef SCORE_DATA_DEPENDENCY_H
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#define SCORE_DATA_DEPENDENCY_H
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#define INSN_NAME_LEN 16
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enum insn_type_for_dependency
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{
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D_pce,
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D_cond_br,
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D_cond_mv,
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D_cached,
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D_cachei,
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D_ldst,
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D_ldcombine,
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D_mtcr,
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D_mfcr,
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D_mfsr,
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D_mftlb,
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D_mtptlb,
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D_mtrtlb,
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D_stlb,
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D_all_insn
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};
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struct insn_to_dependency
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{
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char *insn_name;
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enum insn_type_for_dependency type;
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};
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struct data_dependency
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{
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enum insn_type_for_dependency pre_insn_type;
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char pre_reg[6];
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enum insn_type_for_dependency cur_insn_type;
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char cur_reg[6];
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int bubblenum_7;
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int bubblenum_5;
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int warn_or_error; /* warning - 0; error - 1 */
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};
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static const struct insn_to_dependency insn_to_dependency_table[] =
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{
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/* pce instruction. */
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{"pce", D_pce},
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/* conditional branch instruction. */
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{"bcs", D_cond_br},
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{"bcc", D_cond_br},
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{"bgtu", D_cond_br},
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{"bleu", D_cond_br},
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{"beq", D_cond_br},
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{"bne", D_cond_br},
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{"bgt", D_cond_br},
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{"ble", D_cond_br},
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{"bge", D_cond_br},
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{"blt", D_cond_br},
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{"bmi", D_cond_br},
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{"bpl", D_cond_br},
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{"bvs", D_cond_br},
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{"bvc", D_cond_br},
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{"bcsl", D_cond_br},
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{"bccl", D_cond_br},
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{"bgtul", D_cond_br},
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{"bleul", D_cond_br},
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{"beql", D_cond_br},
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{"bnel", D_cond_br},
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{"bgtl", D_cond_br},
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{"blel", D_cond_br},
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{"bgel", D_cond_br},
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{"bltl", D_cond_br},
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{"bmil", D_cond_br},
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{"bpll", D_cond_br},
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{"bvsl", D_cond_br},
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{"bvcl", D_cond_br},
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{"bcs!", D_cond_br},
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{"bcc!", D_cond_br},
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{"bgtu!", D_cond_br},
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{"bleu!", D_cond_br},
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{"beq!", D_cond_br},
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{"bne!", D_cond_br},
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{"bgt!", D_cond_br},
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{"ble!", D_cond_br},
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{"bge!", D_cond_br},
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{"blt!", D_cond_br},
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{"bmi!", D_cond_br},
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{"bpl!", D_cond_br},
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{"bvs!", D_cond_br},
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{"bvc!", D_cond_br},
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{"brcs", D_cond_br},
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{"brcc", D_cond_br},
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{"brgtu", D_cond_br},
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{"brleu", D_cond_br},
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{"breq", D_cond_br},
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{"brne", D_cond_br},
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{"brgt", D_cond_br},
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{"brle", D_cond_br},
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{"brge", D_cond_br},
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{"brlt", D_cond_br},
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{"brmi", D_cond_br},
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{"brpl", D_cond_br},
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{"brvs", D_cond_br},
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{"brvc", D_cond_br},
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{"brcsl", D_cond_br},
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{"brccl", D_cond_br},
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{"brgtul", D_cond_br},
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{"brleul", D_cond_br},
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{"breql", D_cond_br},
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{"brnel", D_cond_br},
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{"brgtl", D_cond_br},
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{"brlel", D_cond_br},
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{"brgel", D_cond_br},
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{"brltl", D_cond_br},
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{"brmil", D_cond_br},
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{"brpll", D_cond_br},
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{"brvsl", D_cond_br},
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{"brvcl", D_cond_br},
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{"brcs!", D_cond_br},
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{"brcc!", D_cond_br},
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{"brgtu!", D_cond_br},
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{"brleu!", D_cond_br},
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{"breq!", D_cond_br},
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{"brne!", D_cond_br},
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{"brgt!", D_cond_br},
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{"brle!", D_cond_br},
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{"brge!", D_cond_br},
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{"brlt!", D_cond_br},
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{"brmi!", D_cond_br},
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{"brpl!", D_cond_br},
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{"brvs!", D_cond_br},
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{"brvc!", D_cond_br},
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{"brcsl!", D_cond_br},
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{"brccl!", D_cond_br},
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{"brgtul!", D_cond_br},
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{"brleul!", D_cond_br},
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{"breql!", D_cond_br},
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{"brnel!", D_cond_br},
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{"brgtl!", D_cond_br},
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{"brlel!", D_cond_br},
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{"brgel!", D_cond_br},
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{"brltl!", D_cond_br},
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{"brmil!", D_cond_br},
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{"brpll!", D_cond_br},
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{"brvsl!", D_cond_br},
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{"brvcl!", D_cond_br},
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/* conditional move instruction. */
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{"mvcs", D_cond_mv},
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{"mvcc", D_cond_mv},
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{"mvgtu", D_cond_mv},
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{"mvleu", D_cond_mv},
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{"mveq", D_cond_mv},
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{"mvne", D_cond_mv},
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{"mvgt", D_cond_mv},
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{"mvle", D_cond_mv},
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{"mvge", D_cond_mv},
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{"mvlt", D_cond_mv},
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{"mvmi", D_cond_mv},
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{"mvpl", D_cond_mv},
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{"mvvs", D_cond_mv},
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{"mvvc", D_cond_mv},
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/* move spectial instruction. */
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{"mtcr", D_mtcr},
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{"mftlb", D_mftlb},
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{"mtptlb", D_mtptlb},
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{"mtrtlb", D_mtrtlb},
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{"stlb", D_stlb},
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{"mfcr", D_mfcr},
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{"mfsr", D_mfsr},
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/* cache instruction. */
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{"cache 8", D_cached},
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{"cache 9", D_cached},
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{"cache 10", D_cached},
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{"cache 11", D_cached},
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{"cache 12", D_cached},
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{"cache 13", D_cached},
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{"cache 14", D_cached},
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{"cache 24", D_cached},
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{"cache 26", D_cached},
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{"cache 27", D_cached},
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{"cache 29", D_cached},
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{"cache 30", D_cached},
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{"cache 31", D_cached},
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{"cache 0", D_cachei},
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{"cache 1", D_cachei},
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{"cache 2", D_cachei},
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{"cache 3", D_cachei},
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{"cache 4", D_cachei},
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{"cache 16", D_cachei},
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{"cache 17", D_cachei},
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/* load/store instruction. */
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{"lb", D_ldst},
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{"lbu", D_ldst},
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{"lbu!", D_ldst},
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{"lbup!", D_ldst},
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{"lh", D_ldst},
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{"lhu", D_ldst},
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{"lh!", D_ldst},
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{"lhp!", D_ldst},
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{"lw", D_ldst},
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{"lw!", D_ldst},
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{"lwp!", D_ldst},
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{"sb", D_ldst},
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{"sb!", D_ldst},
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{"sbp!", D_ldst},
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{"sh", D_ldst},
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{"sh!", D_ldst},
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{"shp!", D_ldst},
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{"sw", D_ldst},
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{"sw!", D_ldst},
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{"swp!", D_ldst},
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{"alw", D_ldst},
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{"asw", D_ldst},
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{"push!", D_ldst},
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{"pushhi!", D_ldst},
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{"pop!", D_ldst},
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{"pophi!", D_ldst},
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{"ldc1", D_ldst},
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{"ldc2", D_ldst},
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{"ldc3", D_ldst},
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{"stc1", D_ldst},
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{"stc2", D_ldst},
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{"stc3", D_ldst},
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{"scb", D_ldst},
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{"scw", D_ldst},
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{"sce", D_ldst},
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/* load combine instruction. */
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{"lcb", D_ldcombine},
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{"lcw", D_ldcombine},
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{"lce", D_ldcombine},
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};
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static const struct data_dependency data_dependency_table[] =
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{
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/* Condition register. */
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{D_mtcr, "cr1", D_pce, "", 2, 1, 1},
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{D_mtcr, "cr1", D_cond_br, "", 1, 0, 1},
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{D_mtcr, "cr1", D_cond_mv, "", 1, 0, 1},
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/* Status regiser. */
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{D_mtcr, "cr0", D_all_insn, "", 5, 4, 0},
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/* CCR regiser. */
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{D_mtcr, "cr4", D_all_insn, "", 6, 5, 0},
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/* EntryHi/EntryLo register. */
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{D_mftlb, "", D_mtptlb, "", 1, 1, 1},
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{D_mftlb, "", D_mtrtlb, "", 1, 1, 1},
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{D_mftlb, "", D_stlb, "", 1, 1,1},
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{D_mftlb, "", D_mfcr, "cr11", 1, 1, 1},
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{D_mftlb, "", D_mfcr, "cr12", 1, 1, 1},
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/* Index register. */
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{D_stlb, "", D_mtptlb, "", 1, 1, 1},
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{D_stlb, "", D_mftlb, "", 1, 1, 1},
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{D_stlb, "", D_mfcr, "cr8", 2, 2, 1},
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/* Cache. */
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{D_cached, "", D_ldst, "", 1, 1, 0},
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{D_cached, "", D_ldcombine, "", 1, 1, 0},
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{D_cachei, "", D_all_insn, "", 5, 4, 0},
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/* Load combine. */
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{D_ldcombine, "", D_mfsr, "sr1", 3, 3, 1},
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};
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#endif
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