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* config/tc-i386.c (parse_register): If not producing code for
x86_64, reject x86_64 register name matches. (md_assemble): Remove now redundant check for x86_64 regs.
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@ -1,3 +1,9 @@
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2001-10-05 Alan Modra <amodra@bigpond.net.au>
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* config/tc-i386.c (parse_register): If not producing code for
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x86_64, reject x86_64 register name matches.
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(md_assemble): Remove now redundant check for x86_64 regs.
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2001-10-04 Alan Modra <amodra@bigpond.net.au>
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2001-10-04 Alan Modra <amodra@bigpond.net.au>
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* config/tc-ppc.c (md_assemble <DS relocs>): Test ppc_size as well
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* config/tc-ppc.c (md_assemble <DS relocs>): Test ppc_size as well
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@ -1935,19 +1935,6 @@ md_assemble (line)
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}
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}
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}
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}
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if (i.reg_operands && flag_code < CODE_64BIT)
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{
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int op;
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for (op = i.operands; --op >= 0;)
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if ((i.types[op] & Reg)
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&& (i.op[op].regs->reg_flags & (RegRex64|RegRex)))
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{
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as_bad (_("Extended register `%%%s' available only in 64bit mode."),
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i.op[op].regs->reg_name);
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return;
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}
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}
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/* If matched instruction specifies an explicit instruction mnemonic
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/* If matched instruction specifies an explicit instruction mnemonic
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suffix, use it. */
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suffix, use it. */
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if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
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if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
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@ -4531,6 +4518,13 @@ parse_register (reg_string, end_op)
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}
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}
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}
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}
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if (r != NULL
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&& r->reg_flags & (RegRex64|RegRex)
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&& flag_code != CODE_64BIT)
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{
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return (const reg_entry *) NULL;
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}
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return r;
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return r;
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}
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}
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