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Allow lock on cmpxch16b.

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gas/testsuite/

2009-11-19  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/lock-1.s: Add cmpxchg16b test.
	* gas/i386/lock-1-intel.d: Updated.
	* gas/i386/lock-1.d: Likewise.

opcodes/

2009-11-19  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Add IsLockable to cmpxch16b.
	* i386-tbl.h: Regenerated.
This commit is contained in:
H.J. Lu
2009-11-19 15:26:42 +00:00
parent 945ee43039
commit 18d0c96eb9
7 changed files with 19 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
gas/testsuite/ChangeLog
View File

@ -1,3 +1,9 @@
2009-11-19 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/lock-1.s: Add cmpxchg16b test.
* gas/i386/lock-1-intel.d: Updated.
* gas/i386/lock-1.d: Likewise.
2009-11-19 Nick Clifton <nickc@redhat.com> 2009-11-19 Nick Clifton <nickc@redhat.com>
PR binutils/10924 PR binutils/10924

2
gas/testsuite/gas/i386/x86-64-lock-1-intel.d
View File

@ -22,6 +22,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f0 0f ba 2b 64 lock bts DWORD PTR \[rbx\],0x64 [ ]*[a-f0-9]+: f0 0f ba 2b 64 lock bts DWORD PTR \[rbx\],0x64
[ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg DWORD PTR \[rbx\],eax [ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg DWORD PTR \[rbx\],eax
[ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b QWORD PTR \[rbx\] [ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b QWORD PTR \[rbx\]
[ ]*[a-f0-9]+: f0 48 0f c7 0b lock cmpxchg16b OWORD PTR \[rbx\]
[ ]*[a-f0-9]+: f0 ff 0b lock dec DWORD PTR \[rbx\] [ ]*[a-f0-9]+: f0 ff 0b lock dec DWORD PTR \[rbx\]
[ ]*[a-f0-9]+: f0 ff 03 lock inc DWORD PTR \[rbx\] [ ]*[a-f0-9]+: f0 ff 03 lock inc DWORD PTR \[rbx\]
[ ]*[a-f0-9]+: f0 f7 1b lock neg DWORD PTR \[rbx\] [ ]*[a-f0-9]+: f0 f7 1b lock neg DWORD PTR \[rbx\]
@ -51,6 +52,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f0 0f ba 2b 64 lock bts DWORD PTR \[rbx\],0x64 [ ]*[a-f0-9]+: f0 0f ba 2b 64 lock bts DWORD PTR \[rbx\],0x64
[ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg DWORD PTR \[rbx\],eax [ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg DWORD PTR \[rbx\],eax
[ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b QWORD PTR \[rbx\] [ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b QWORD PTR \[rbx\]
[ ]*[a-f0-9]+: f0 48 0f c7 0b lock cmpxchg16b OWORD PTR \[rbx\]
[ ]*[a-f0-9]+: f0 ff 0b lock dec DWORD PTR \[rbx\] [ ]*[a-f0-9]+: f0 ff 0b lock dec DWORD PTR \[rbx\]
[ ]*[a-f0-9]+: f0 ff 03 lock inc DWORD PTR \[rbx\] [ ]*[a-f0-9]+: f0 ff 03 lock inc DWORD PTR \[rbx\]
[ ]*[a-f0-9]+: f0 f7 1b lock neg DWORD PTR \[rbx\] [ ]*[a-f0-9]+: f0 f7 1b lock neg DWORD PTR \[rbx\]

2
gas/testsuite/gas/i386/x86-64-lock-1.d
View File

@ -21,6 +21,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f0 0f ba 2b 64 lock btsl \$0x64,\(%rbx\) [ ]*[a-f0-9]+: f0 0f ba 2b 64 lock btsl \$0x64,\(%rbx\)
[ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg %eax,\(%rbx\) [ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg %eax,\(%rbx\)
[ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b \(%rbx\) [ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b \(%rbx\)
[ ]*[a-f0-9]+: f0 48 0f c7 0b lock cmpxchg16b \(%rbx\)
[ ]*[a-f0-9]+: f0 ff 0b lock decl \(%rbx\) [ ]*[a-f0-9]+: f0 ff 0b lock decl \(%rbx\)
[ ]*[a-f0-9]+: f0 ff 03 lock incl \(%rbx\) [ ]*[a-f0-9]+: f0 ff 03 lock incl \(%rbx\)
[ ]*[a-f0-9]+: f0 f7 1b lock negl \(%rbx\) [ ]*[a-f0-9]+: f0 f7 1b lock negl \(%rbx\)
@ -50,6 +51,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f0 0f ba 2b 64 lock btsl \$0x64,\(%rbx\) [ ]*[a-f0-9]+: f0 0f ba 2b 64 lock btsl \$0x64,\(%rbx\)
[ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg %eax,\(%rbx\) [ ]*[a-f0-9]+: f0 0f b1 03 lock cmpxchg %eax,\(%rbx\)
[ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b \(%rbx\) [ ]*[a-f0-9]+: f0 0f c7 0b lock cmpxchg8b \(%rbx\)
[ ]*[a-f0-9]+: f0 48 0f c7 0b lock cmpxchg16b \(%rbx\)
[ ]*[a-f0-9]+: f0 ff 0b lock decl \(%rbx\) [ ]*[a-f0-9]+: f0 ff 0b lock decl \(%rbx\)
[ ]*[a-f0-9]+: f0 ff 03 lock incl \(%rbx\) [ ]*[a-f0-9]+: f0 ff 03 lock incl \(%rbx\)
[ ]*[a-f0-9]+: f0 f7 1b lock negl \(%rbx\) [ ]*[a-f0-9]+: f0 f7 1b lock negl \(%rbx\)

2
gas/testsuite/gas/i386/x86-64-lock-1.s
View File

@ -16,6 +16,7 @@ foo:
lock bts $0x64, (%rbx) lock bts $0x64, (%rbx)
lock cmpxchg %eax,(%rbx) lock cmpxchg %eax,(%rbx)
lock cmpxchg8b (%rbx) lock cmpxchg8b (%rbx)
lock cmpxchg16b (%rbx)
lock decl (%rbx) lock decl (%rbx)
lock incl (%rbx) lock incl (%rbx)
lock negl (%rbx) lock negl (%rbx)
@ -47,6 +48,7 @@ foo:
lock bts DWORD PTR [rbx],0x64 lock bts DWORD PTR [rbx],0x64
lock cmpxchg DWORD PTR [rbx],eax lock cmpxchg DWORD PTR [rbx],eax
lock cmpxchg8b QWORD PTR [rbx] lock cmpxchg8b QWORD PTR [rbx]
lock cmpxchg16b OWORD PTR [rbx]
lock dec DWORD PTR [rbx] lock dec DWORD PTR [rbx]
lock inc DWORD PTR [rbx] lock inc DWORD PTR [rbx]
lock neg DWORD PTR [rbx] lock neg DWORD PTR [rbx]

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2009-11-19 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add IsLockable to cmpxch16b.
* i386-tbl.h: Regenerated.
2009-11-19 Nick Clifton <nickc@redhat.com> 2009-11-19 Nick Clifton <nickc@redhat.com>
PR binutils/10924 PR binutils/10924

2
opcodes/i386-opc.tbl
View File

@ -1505,7 +1505,7 @@ addsubpd, 2, 0x66d0, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|
addsubpd, 2, 0x660fd0, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } addsubpd, 2, 0x660fd0, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
addsubps, 2, 0xf2d0, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } addsubps, 2, 0xf2d0, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
addsubps, 2, 0xf20fd0, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } addsubps, 2, 0xf20fd0, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
cmpxchg16b, 1, 0xfc7, 0x1, 2, CpuSSE3|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|NoAVX, { Oword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } cmpxchg16b, 1, 0xfc7, 0x1, 2, CpuSSE3|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|NoAVX|IsLockable, { Oword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S }
fisttp, 1, 0xdf, 0x1, 1, CpuFISTTP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf|NoAVX, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } fisttp, 1, 0xdf, 0x1, 1, CpuFISTTP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf|NoAVX, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
fisttp, 1, 0xdd, 0x1, 1, CpuFISTTP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } fisttp, 1, 0xdd, 0x1, 1, CpuFISTTP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
fisttpll, 1, 0xdd, 0x1, 1, CpuFISTTP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } fisttpll, 1, 0xdd, 0x1, 1, CpuFISTTP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }

2
opcodes/i386-tbl.h
View File

@ -14962,7 +14962,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0 } }, 0, 1, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 }, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,