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* config/tc-mips.c (macro): If $0 is destination of divide, just

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generate the simple machine instruction, for compatibility with
	the MIPS assembler.
This commit is contained in:
Ian Lance Taylor
1993-09-02 14:46:54 +00:00
parent a9c686adf5
commit 1849d6464f
2 changed files with 40 additions and 0 deletions
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6
gas/ChangeLog
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@ -1,3 +1,9 @@
Thu Sep 2 10:43:57 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com)
* config/tc-mips.c (macro): If $0 is destination of divide, just
generate the simple machine instruction, for compatibility with
the MIPS assembler.
Wed Sep 1 15:56:42 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) Wed Sep 1 15:56:42 1993 Ken Raeburn (raeburn@cambridge.cygnus.com)
* write.c (write_relocs) [RELOC_EXPANSION_POSSIBLE]: Declare * write.c (write_relocs) [RELOC_EXPANSION_POSSIBLE]: Declare

34
gas/config/tc-mips.c
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@ -736,6 +736,25 @@ append_insn (ip, address_expr, reloc_type)
((prev_insn.insn_opcode >> OP_SH_RD) ((prev_insn.insn_opcode >> OP_SH_RD)
& OP_MASK_RD), & OP_MASK_RD),
0)) 0))
/* If the branch writes a register that the previous
instruction sets, we can not swap (we know that
branches write only to RD or to $31). */
|| ((prev_insn.insn_mo->pinfo & INSN_WRITE_GPR_T)
&& (((ip->insn_mo->pinfo & INSN_WRITE_GPR_D)
&& (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
== ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
|| ((ip->insn_mo->pinfo & INSN_WRITE_GPR_31)
&& (((prev_insn.insn_opcode >> OP_SH_RT)
& OP_MASK_RT)
== 31))))
|| ((prev_insn.insn_mo->pinfo & INSN_WRITE_GPR_D)
&& (((ip->insn_mo->pinfo & INSN_WRITE_GPR_D)
&& (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
== ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
|| ((ip->insn_mo->pinfo & INSN_WRITE_GPR_31)
&& (((prev_insn.insn_opcode >> OP_SH_RD)
& OP_MASK_RD)
== 31))))
/* If the branch writes a register that the previous /* If the branch writes a register that the previous
instruction reads, we can not swap (we know that instruction reads, we can not swap (we know that
branches only write to RD or to $31). */ branches only write to RD or to $31). */
@ -1745,6 +1764,15 @@ macro (ip)
macro_build (&icnt, NULL, "break", "c", 7); macro_build (&icnt, NULL, "break", "c", 7);
return; return;
} }
if (dreg == 0)
{
/* The MIPS assembler treats a destination of $0 as a
request for just the machine instruction. */
macro_build (&icnt, NULL,
dbl ? "ddiv" : "div",
"s,t", sreg, treg);
return;
}
mips_emit_delays (); mips_emit_delays ();
++mips_noreorder; ++mips_noreorder;
@ -3923,6 +3951,7 @@ mips_align (to, fill)
assert (S_GET_SEGMENT (insn_label) == now_seg); assert (S_GET_SEGMENT (insn_label) == now_seg);
insn_label->sy_frag = frag_now; insn_label->sy_frag = frag_now;
S_SET_VALUE (insn_label, frag_now_fix ()); S_SET_VALUE (insn_label, frag_now_fix ());
insn_label = NULL;
} }
} }
@ -3985,6 +4014,7 @@ s_stringer (append_zero)
int append_zero; int append_zero;
{ {
mips_emit_delays (); mips_emit_delays ();
insn_label = NULL;
stringer (append_zero); stringer (append_zero);
} }
@ -4041,6 +4071,7 @@ s_cons (log_size)
mips_emit_delays (); mips_emit_delays ();
if (log_size > 0 && auto_align) if (log_size > 0 && auto_align)
mips_align (log_size, 0); mips_align (log_size, 0);
insn_label = NULL;
cons (1 << log_size); cons (1 << log_size);
} }
@ -4084,6 +4115,8 @@ s_float_cons (type)
else else
mips_align (2, 0); mips_align (2, 0);
insn_label = NULL;
float_cons (type); float_cons (type);
} }
@ -4172,6 +4205,7 @@ s_mips_space (param)
int param; int param;
{ {
mips_emit_delays (); mips_emit_delays ();
insn_label = NULL;
s_space (param); s_space (param);
} }