mirror of
https://github.com/espressif/binutils-gdb.git
synced 2025-08-02 02:35:00 +08:00
2011-01-08 Michael Snyder <msnyder@vmware.com>
* h8300-tdep.c: Comment cleanup, mostly periods and spaces. * hppa-hpux-tdep.c: Ditto. * hppa-linux-nat.c: Ditto. * hppa-linux-tdep.c: Ditto. * hppanbsd-tdep.c: Ditto. * hppa-tdep.c: Ditto. * hppa-tdep.h: Ditto. * hpux-thread.c: Ditto. * i386-cygwin-tdep.c: Ditto. * i386-darwin-nat.c: Ditto. * i386gnu-nat.c: Ditto. * i386-linux-nat.c: Ditto. * i386-linux-tdep.c: Ditto. * i386-nat.c: Ditto. * i386-nat.h: Ditto. * i386nbsd-tdep.c: Ditto. * i386-sol2-nat.c: Ditto. * i386-stub.c: Ditto. * i386-tdep.c: Ditto. * i386-tdep.h: Ditto. * i387-tdep.c: Ditto. * ia64-linux-nat.c: Ditto. * ia64-linux-tdep.c: Ditto. * ia64-tdep.c: Ditto. * infcall.c: Ditto. * infcall.h: Ditto. * infcmd.c: Ditto. * inferior.c: Ditto. * inferior.h: Ditto. * infloop.c: Ditto. * inflow.c: Ditto. * infrun.c: Ditto. * interps.c: Ditto. * interps.h: Ditto. * iq2000-tdep.c: Ditto. * irix5-nat.c: Ditto. * jit.c: Ditto. * jit.h: Ditto. * jv-exp.y: Ditto. * jv-lang.c: Ditto. * jv-lang.h: Ditto. * jv-typeprint.c: Ditto. * jv-valprint.c: Ditto. * language.c: Ditto. * language.h: Ditto. * linespec.c: Ditto. * linux-fork.c: Ditto. * linux-nat.c: Ditto. * linux-thread-db.c: Ditto. * lm32-tdep.c: Ditto.
This commit is contained in:
@ -48,7 +48,7 @@
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struct gdbarch_tdep
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{
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/* gdbarch target dependent data here. Currently unused for LM32. */
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/* gdbarch target dependent data here. Currently unused for LM32. */
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};
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struct lm32_frame_cache
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@ -144,7 +144,7 @@ lm32_analyze_prologue (struct gdbarch *gdbarch,
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if ((LM32_OPCODE (instruction) == OP_SW)
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&& (LM32_REG0 (instruction) == SIM_LM32_SP_REGNUM))
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{
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/* Any stack displaced store is likely part of the prologue.
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/* Any stack displaced store is likely part of the prologue.
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Record that the register is being saved, and the offset
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into the stack. */
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info->saved_regs[LM32_REG1 (instruction)].addr =
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@ -153,7 +153,7 @@ lm32_analyze_prologue (struct gdbarch *gdbarch,
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else if ((LM32_OPCODE (instruction) == OP_ADDI)
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&& (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
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{
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/* An add to the SP is likely to be part of the prologue.
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/* An add to the SP is likely to be part of the prologue.
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Adjust stack size by whatever the instruction adds to the sp. */
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info->size -= LM32_IMM16 (instruction);
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}
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@ -172,7 +172,8 @@ lm32_analyze_prologue (struct gdbarch *gdbarch,
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}
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else
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{
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/* Any other instruction is likely not to be part of the prologue. */
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/* Any other instruction is likely not to be part of the
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prologue. */
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break;
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}
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}
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@ -336,8 +337,8 @@ lm32_extract_return_value (struct type *type, struct regcache *regcache,
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}
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else
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{
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/* Aggregate types greater than a single register are returned in memory.
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FIXME: Unless they are only 2 regs?. */
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/* Aggregate types greater than a single register are returned
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in memory. FIXME: Unless they are only 2 regs?. */
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regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
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return_buffer = l;
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read_memory (return_buffer, valbuf, TYPE_LENGTH (type));
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@ -463,7 +464,8 @@ lm32_frame_cache (struct frame_info *this_frame, void **this_prologue_cache)
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converted into a request for the RA register. */
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info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM];
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/* The previous frame's SP needed to be computed. Save the computed value. */
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/* The previous frame's SP needed to be computed. Save the computed
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value. */
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trad_frame_set_value (info->saved_regs, SIM_LM32_SP_REGNUM, prev_sp);
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return info;
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