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x86: Add int1 as one byte opcode 0xf1

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Also change the x86 disassembler to disassemble 0xf1 as int1, instead of
icebp.

gas/

	PR gas/28088
	* testsuite/gas/i386/opcode.s: Add int1.
	* testsuite/gas/i386/x86-64-opcode.s: Add int1, int3 and int.
	* testsuite/gas/i386/opcode-intel.d: Updated.
	* testsuite/gas/i386/opcode-suffix.d: Likewise.
	* testsuite/gas/i386/opcode.d: Likewise.
	* testsuite/gas/i386/x86-64-opcode.d: Likewise.

opcodes/

	PR gas/28088
	* i386-dis.c (dis386): Replace icebp with int1.
	* i386-opc.tbl: Add int1.
	* i386-tbl.h: Regenerate.
This commit is contained in:
H.J. Lu
2021-07-14 14:17:48 -07:00
parent 9cce9fab90
commit 154b353f68
9 changed files with 27 additions and 1 deletions
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1
gas/testsuite/gas/i386/opcode-intel.d
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@ -588,6 +588,7 @@ Disassembly of section .text:
*[0-9a-f]+: 85 c3 [ ]*test[ ]+ebx,eax *[0-9a-f]+: 85 c3 [ ]*test[ ]+ebx,eax
*[0-9a-f]+: 85 d8 [ ]*test[ ]+eax,ebx *[0-9a-f]+: 85 d8 [ ]*test[ ]+eax,ebx
*[0-9a-f]+: 85 18 [ ]*test[ ]+(DWORD PTR )?\[eax\],ebx *[0-9a-f]+: 85 18 [ ]*test[ ]+(DWORD PTR )?\[eax\],ebx
*[0-9a-f]+: f1[ ]+int1[ ]+
[ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovp edx,DWORD PTR \[eax-0x6f6f6f70\] [ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovp edx,DWORD PTR \[eax-0x6f6f6f70\]
[ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp edx,DWORD PTR \[eax-0x6f6f6f70\] [ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp edx,DWORD PTR \[eax-0x6f6f6f70\]
[ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp dx,WORD PTR \[eax-0x6f6f6f70\] [ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp dx,WORD PTR \[eax-0x6f6f6f70\]

1
gas/testsuite/gas/i386/opcode-suffix.d
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@ -588,6 +588,7 @@ Disassembly of section .text:
*[0-9a-f]+: 85 c3 [ ]*testl[ ]+%eax,%ebx *[0-9a-f]+: 85 c3 [ ]*testl[ ]+%eax,%ebx
*[0-9a-f]+: 85 d8 [ ]*testl[ ]+%ebx,%eax *[0-9a-f]+: 85 d8 [ ]*testl[ ]+%ebx,%eax
*[0-9a-f]+: 85 18 [ ]*testl[ ]+%ebx,\(%eax\) *[0-9a-f]+: 85 18 [ ]*testl[ ]+%ebx,\(%eax\)
*[0-9a-f]+: f1[ ]+int1[ ]+
[ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovpl -0x6f6f6f70\(%eax\),%edx [ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovpl -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnpl -0x6f6f6f70\(%eax\),%edx [ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnpl -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovpw -0x6f6f6f70\(%eax\),%dx [ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovpw -0x6f6f6f70\(%eax\),%dx

1
gas/testsuite/gas/i386/opcode.d
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@ -587,6 +587,7 @@ Disassembly of section .text:
9f5: 85 c3 [ ]*test %eax,%ebx 9f5: 85 c3 [ ]*test %eax,%ebx
9f7: 85 d8 [ ]*test %ebx,%eax 9f7: 85 d8 [ ]*test %ebx,%eax
9f9: 85 18 [ ]*test %ebx,\(%eax\) 9f9: 85 18 [ ]*test %ebx,\(%eax\)
9fb: f1 [ ]*int1
[ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%edx [ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp -0x6f6f6f70\(%eax\),%edx [ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%dx [ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%dx

2
gas/testsuite/gas/i386/opcode.s
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@ -585,6 +585,8 @@ foo:
test %ebx,%eax test %ebx,%eax
test (%eax),%ebx test (%eax),%ebx
int1
cmovpe 0x90909090(%eax),%edx cmovpe 0x90909090(%eax),%edx
cmovpo 0x90909090(%eax),%edx cmovpo 0x90909090(%eax),%edx
cmovpe 0x90909090(%eax),%dx cmovpe 0x90909090(%eax),%dx

3
gas/testsuite/gas/i386/x86-64-opcode.d
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@ -325,6 +325,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 0f 07 sysretq * [ ]*[a-f0-9]+: 48 0f 07 sysretq *
[ ]*[a-f0-9]+: 0f 01 f8 swapgs [ ]*[a-f0-9]+: 0f 01 f8 swapgs
[ ]*[a-f0-9]+: 66 68 22 22 pushw \$0x2222 [ ]*[a-f0-9]+: 66 68 22 22 pushw \$0x2222
[ ]*[a-f0-9]+: f1 int1 +
[ ]*[a-f0-9]+: cc int3 +
[ ]*[a-f0-9]+: cd 90 int \$0x90
[ ]*[a-f0-9]+: f6 c9 01 test \$(0x)?0*1,%cl [ ]*[a-f0-9]+: f6 c9 01 test \$(0x)?0*1,%cl
[ ]*[a-f0-9]+: 66 f7 c9 02 00 test \$(0x)?0*2,%cx [ ]*[a-f0-9]+: 66 f7 c9 02 00 test \$(0x)?0*2,%cx
[ ]*[a-f0-9]+: f7 c9 04 00 00 00 test \$(0x)?0*4,%ecx [ ]*[a-f0-9]+: f7 c9 04 00 00 00 test \$(0x)?0*4,%ecx

4
gas/testsuite/gas/i386/x86-64-opcode.s
View File

@ -454,6 +454,10 @@
pushw $0x2222 pushw $0x2222
int1
int3
int $0x90
.byte 0xf6, 0xc9, 0x01 .byte 0xf6, 0xc9, 0x01
.byte 0x66, 0xf7, 0xc9, 0x02, 0x00 .byte 0x66, 0xf7, 0xc9, 0x02, 0x00
.byte 0xf7, 0xc9, 0x04, 0x00, 0x00, 0x00 .byte 0xf7, 0xc9, 0x04, 0x00, 0x00, 0x00

2
opcodes/i386-dis.c
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@ -1965,7 +1965,7 @@ static const struct dis386 dis386[] = {
{ "outG", { indirDX, zAX }, 0 }, { "outG", { indirDX, zAX }, 0 },
/* f0 */ /* f0 */
{ Bad_Opcode }, /* lock prefix */ { Bad_Opcode }, /* lock prefix */
{ "icebp", { XX }, 0 }, { "int1", { XX }, 0 },
{ Bad_Opcode }, /* repne */ { Bad_Opcode }, /* repne */
{ Bad_Opcode }, /* repz */ { Bad_Opcode }, /* repz */
{ "hlt", { XX }, 0 }, { "hlt", { XX }, 0 },

1
opcodes/i386-opc.tbl
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@ -537,6 +537,7 @@ bts, 0xfba, 5, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8, Reg
// See gas/config/tc-i386.c for conversion of 'int $3' into the special // See gas/config/tc-i386.c for conversion of 'int $3' into the special
// int 3 insn. // int 3 insn.
int, 0xcd, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8 } int, 0xcd, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8 }
int1, 0xf1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
int3, 0xcc, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} int3, 0xcc, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
into, 0xce, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} into, 0xce, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
iret, 0xcf, None, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, {} iret, 0xcf, None, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, {}

13
opcodes/i386-tbl.h
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@ -5229,6 +5229,19 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } }, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0 } } } }, 0, 0, 0, 0, 0, 0, 0 } } } },
{ "int1", 0xf1, None, 0,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0 } } } },
{ "int3", 0xcc, None, 0, { "int3", 0xcc, None, 0,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,