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* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code
into single PKE-style vu.[ch].
[ChangeLog]
Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
start-sanitize-sky
* Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
* interp.c (sim_{load,store}_register): Use new vu[01]_device
static to access VU registers.
(decode_coproc): Added skeleton of sky COP2 (VU) instruction
decoding. Work in progress.
* mips.igen (LDCzz, SDCzz): Removed *5900 case for this
overlapping/redundant bit pattern.
(LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
progress.
* sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
status register.
end-sanitize-sky
* interp.c (cop_lq, cop_sq): New functions for future 128-bit
access to coprocessor registers.
* sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
[ChangeLog.sky]
* sky-engine.c (engine_run): Adapted from vu[01] -> vu merge.
* sky-hardware.c (register_devices): Ditto
* sky-pke.c (pke_fifo_*): Made these functions private again, now
that the GPUIF code does not use them.
* sky-pke.h (pke_fifo_*): Removed newly private declarations.
* sky-vu.c (*): Major rework: merge of old sky-vu0.c and
sky-vu1.c. Management of two VU devices parallels two PKEs.
Work in progress.
* sky-vu.h (*): Other half of merge.
(vu_device): New struct, parallel to pke_device.
This commit is contained in:
Frank Ch. Eigler
@ -14,8 +14,7 @@
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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$Revision$
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$Author$
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$Date$
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$Date$
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NOTEs:
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@ -39,6 +38,14 @@ code on the hardware.
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#include "sim-options.h"
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#include "sim-assert.h"
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/* start-sanitize-sky */
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#ifdef TARGET_SKY
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#include "sky-vu.h"
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#include "sky-vpe.h"
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#include "sky-libvpe.h"
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#endif
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/* end-sanitize-sky */
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#include "config.h"
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#include <stdio.h>
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@ -154,6 +161,7 @@ static void ColdReset PARAMS((SIM_DESC sd));
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#define MONITOR_BASE (0xBFC00000)
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#define MONITOR_SIZE (1 << 11)
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#define MEM_SIZE (2 << 20)
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/* start-sanitize-sky */
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#ifdef TARGET_SKY
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#undef MEM_SIZE
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@ -672,7 +680,7 @@ sim_store_register (sd,rn,memory,length)
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rn = rn - NUM_R5900_REGS;
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if (rn < NUM_VU_INTEGER_REGS)
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size = write_vu_int_reg (&(vu0_state.regs), rn, memory);
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size = write_vu_int_reg (& vu0_device.state->regs, rn, memory);
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else if( rn < NUM_VU_REGS )
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vu_regs[0].f[rn - NUM_VU_INTEGER_REGS]
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= T2H_4( *(unsigned int *) memory );
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@ -680,7 +688,7 @@ sim_store_register (sd,rn,memory,length)
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rn = rn - NUM_VU_REGS;
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if( rn < NUM_VU_INTEGER_REGS )
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size = write_vu_int_reg (&(vu1_state.regs), rn, memory);
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size = write_vu_int_reg (& vu1_device.state->regs, rn, memory);
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else if( rn < NUM_VU_REGS )
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vu_regs[1].f[rn - NUM_VU_INTEGER_REGS]
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= T2H_4( *(unsigned int *) memory );
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@ -768,7 +776,7 @@ sim_fetch_register (sd,rn,memory,length)
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rn = rn - NUM_R5900_REGS;
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if (rn < NUM_VU_INTEGER_REGS)
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size = read_vu_int_reg (&(vu0_state.regs), rn, memory);
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size = read_vu_int_reg (& vu0_device.state->regs, rn, memory);
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else if (rn < NUM_VU_REGS)
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*((unsigned int *) memory)
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= H2T_4( vu_regs[0].f[rn - NUM_VU_INTEGER_REGS] );
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@ -777,7 +785,7 @@ sim_fetch_register (sd,rn,memory,length)
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rn = rn - NUM_VU_REGS;
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if (rn < NUM_VU_INTEGER_REGS)
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size = read_vu_int_reg (&(vu1_state.regs), rn, memory);
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size = read_vu_int_reg (& vu1_device.state->regs, rn, memory);
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else if (rn < NUM_VU_REGS)
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(*(unsigned int *) memory)
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= H2T_4( vu_regs[1].f[rn - NUM_VU_INTEGER_REGS] );
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@ -3239,6 +3247,33 @@ cop_ld (SIM_DESC sd,
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return;
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}
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void
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cop_lq (SIM_DESC sd,
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sim_cpu *cpu,
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address_word cia,
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int coproc_num,
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int coproc_reg,
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unsigned128 memword)
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{
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switch (coproc_num)
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{
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/* start-sanitize-sky */
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case 2:
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/* XXX COP2 */
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break;
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/* end-sanitize-sky */
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default:
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sim_io_printf(sd,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n",
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coproc_num,coproc_reg,pr_addr(cia));
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break;
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}
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return;
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}
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unsigned int
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cop_sw (SIM_DESC sd,
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sim_cpu *cpu,
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@ -3298,6 +3333,33 @@ cop_sd (SIM_DESC sd,
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return(value);
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}
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unsigned128
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cop_sq (SIM_DESC sd,
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sim_cpu *cpu,
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address_word cia,
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int coproc_num,
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int coproc_reg)
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{
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unsigned128 value = {0, 0};
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switch (coproc_num)
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{
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/* start-sanitize-sky */
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case 2:
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/* XXX COP2 */
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break;
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/* end-sanitize-sky */
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default:
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sim_io_printf(sd,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",
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coproc_num,coproc_reg,pr_addr(cia));
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break;
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}
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return(value);
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}
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void
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decode_coproc (SIM_DESC sd,
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sim_cpu *cpu,
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@ -3439,9 +3501,140 @@ decode_coproc (SIM_DESC sd,
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break;
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case 2: /* undefined co-processor */
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sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
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break;
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{
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int handle = 0;
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/* start-sanitize-sky */
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/* On the R5900, this refers to a "VU" vector co-processor. */
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int i_25_21 = (instruction >> 21) & 0x1f;
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int i_20_16 = (instruction >> 16) & 0x1f;
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int i_15_11 = (instruction >> 11) & 0x1f;
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int i_15_0 = instruction & 0xffff;
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int i_10_1 = (instruction >> 1) & 0x3ff;
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int interlock = instruction & 0x01;
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unsigned_4 vpe_status = sim_core_read_aligned_4 (cpu, cia, read_map, VPE0_STAT);
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int vpe_busy = (vpe_status & 0x00000001);
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/* setup for semantic.c-like actions below */
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typedef unsigned_4 instruction_word;
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int CIA = cia;
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int NIA = cia + 4;
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sim_cpu* CPU_ = cpu;
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handle = 1;
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/* test COP2 usability */
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if(! (SR & status_CU2))
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{
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SignalException(CoProcessorUnusable,instruction);
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/* NOTREACHED */
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}
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/* classify & execute basic COP2 instructions */
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if(i_25_21 == 0x08 && i_20_16 == 0x00) /* BC2F */
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{
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address_word offset = EXTEND16(i_15_0) << 2;
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if(! vpe_busy) DELAY_SLOT(cia + 4 + offset);
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}
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else if(i_25_21 == 0x08 && i_20_16==0x02) /* BC2FL */
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{
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address_word offset = EXTEND16(i_15_0) << 2;
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if(! vpe_busy) DELAY_SLOT(cia + 4 + offset);
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else NULLIFY_NEXT_INSTRUCTION();
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}
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else if(i_25_21 == 0x08 && i_20_16 == 0x01) /* BC2T */
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{
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address_word offset = EXTEND16(i_15_0) << 2;
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if(vpe_busy) DELAY_SLOT(cia + 4 + offset);
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}
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else if(i_25_21 == 0x08 && i_20_16 == 0x03) /* BC2TL */
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{
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address_word offset = EXTEND16(i_15_0) << 2;
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if(vpe_busy) DELAY_SLOT(cia + 4 + offset);
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else NULLIFY_NEXT_INSTRUCTION();
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}
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else if((i_25_21 == 0x02 && i_10_1 == 0x000) || /* CFC2 */
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(i_25_21 == 0x06 && i_10_1 == 0x000)) /* CTC2 */
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{
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int rt = i_20_16;
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int id = i_15_11;
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int to_vu = (i_25_21 == 0x06); /* transfer direction */
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address_word vu_cr_addr; /* VU control register address */
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if(interlock)
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while(vpe_busy)
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{
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vu0_issue(sd); /* advance one clock cycle */
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vpe_status = sim_core_read_aligned_4 (cpu, cia, read_map, VPE0_STAT);
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vpe_busy = vpe_status & 0x00000001;
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}
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/* compute VU register address */
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vu_cr_addr = VU0_MST + (id * 16);
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/* read or write word */
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if(to_vu) /* CTC2 */
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{
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unsigned_4 data = GPR[rt];
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sim_core_write_aligned_4(cpu, cia, write_map, vu_cr_addr, data);
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}
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else /* CFC2 */
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{
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unsigned_4 data = sim_core_read_aligned_4(cpu, cia, read_map, vu_cr_addr);
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GPR[rt] = EXTEND64(data);
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}
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}
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else if((i_25_21 == 0x01) || /* QMFC2 */
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(i_25_21 == 0x05)) /* QMTC2 */
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{
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int rt = i_20_16;
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int id = i_15_11;
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int to_vu = (i_25_21 == 0x05); /* transfer direction */
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address_word vu_cr_addr; /* VU control register address */
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if(interlock)
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while(vpe_busy)
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{
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vu0_issue(sd); /* advance one clock cycle */
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vpe_status = sim_core_read_aligned_4 (cpu, cia, read_map, VPE0_STAT);
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vpe_busy = vpe_status & 0x00000001;
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}
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/* compute VU register address */
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vu_cr_addr = VU0_VF00 + (id * 16);
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/* read or write word */
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if(to_vu) /* CTC2 */
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{
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unsigned_4 data = GPR[rt];
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sim_core_write_aligned_4(cpu, cia, write_map, vu_cr_addr, data);
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}
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else /* CFC2 */
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{
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unsigned_4 data = sim_core_read_aligned_4(cpu, cia, read_map, vu_cr_addr);
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GPR[rt] = EXTEND64(data);
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}
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}
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/* other COP2 instructions */
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else
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{
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SignalException(ReservedInstruction,instruction);
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/* NOTREACHED */
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}
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/* cleanup for semantic.c-like actions above */
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PC = NIA;
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/* end-sanitize-sky */
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if(! handle)
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{
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sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
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instruction,pr_addr(cia));
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}
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}
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break;
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case 1: /* should not occur (FPU co-processor) */
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case 3: /* should not occur (FPU co-processor) */
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SignalException(ReservedInstruction,instruction);
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@ -3451,6 +3644,7 @@ decode_coproc (SIM_DESC sd,
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return;
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}
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/*-- instruction simulation -------------------------------------------------*/
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/* When the IGEN simulator is being built, the function below is be
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