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[binutils][aarch64] New SVE_Zm3_11_INDEX operand.
Introduce new operand SVE_Zm3_11_INDEX that indicates a register between z0-z7 stored in bits 18-16 and an index stored in bits 20-19:11. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_Zm3_11_INDEX. (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX. (fields): Handle SVE_i3l and SVE_i3h2 fields. * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2 fields. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
This commit is contained in:
Matthew Malcomson
@ -1,3 +1,8 @@
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX
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operand.
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand.
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@ -5637,6 +5637,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_SVE_Zm3_INDEX:
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case AARCH64_OPND_SVE_Zm3_22_INDEX:
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case AARCH64_OPND_SVE_Zm3_11_INDEX:
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case AARCH64_OPND_SVE_Zm4_INDEX:
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case AARCH64_OPND_SVE_Zn_INDEX:
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reg_type = REG_TYPE_ZN;
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@ -1,3 +1,7 @@
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand.
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass.
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@ -412,6 +412,7 @@ enum aarch64_opnd
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AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
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AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
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AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
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AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */
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AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
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AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
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AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
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@ -1,3 +1,16 @@
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Regenerated.
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* aarch64-opc-2.c: Regenerated.
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* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
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for SVE_Zm3_11_INDEX.
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(aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
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(fields): Handle SVE_i3l and SVE_i3h2 fields.
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* aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
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fields.
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* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
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@ -647,8 +647,8 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 189:
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case 190:
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case 191:
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case 195:
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case 198:
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case 196:
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case 199:
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return aarch64_ins_regno (self, info, code, inst, errors);
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case 14:
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return aarch64_ins_reg_extended (self, info, code, inst, errors);
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@ -660,7 +660,7 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 32:
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case 33:
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case 34:
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case 201:
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case 202:
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return aarch64_ins_reglane (self, info, code, inst, errors);
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case 35:
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return aarch64_ins_reglist (self, info, code, inst, errors);
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@ -704,7 +704,7 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 180:
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case 181:
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case 182:
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case 200:
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case 201:
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return aarch64_ins_imm (self, info, code, inst, errors);
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case 43:
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case 44:
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@ -848,11 +848,12 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 192:
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case 193:
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case 194:
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case 195:
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return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
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case 196:
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return aarch64_ins_sve_index (self, info, code, inst, errors);
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case 197:
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case 199:
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return aarch64_ins_sve_index (self, info, code, inst, errors);
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case 198:
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case 200:
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return aarch64_ins_sve_reglist (self, info, code, inst, errors);
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default: assert (0); abort ();
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}
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@ -20078,8 +20078,8 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 189:
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case 190:
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case 191:
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case 195:
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case 198:
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case 196:
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case 199:
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return aarch64_ext_regno (self, info, code, inst, errors);
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case 9:
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return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
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@ -20095,7 +20095,7 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 32:
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case 33:
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case 34:
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case 201:
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case 202:
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return aarch64_ext_reglane (self, info, code, inst, errors);
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case 35:
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return aarch64_ext_reglist (self, info, code, inst, errors);
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@ -20140,7 +20140,7 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 180:
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case 181:
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case 182:
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case 200:
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case 201:
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return aarch64_ext_imm (self, info, code, inst, errors);
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case 43:
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case 44:
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@ -20286,11 +20286,12 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 192:
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case 193:
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case 194:
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case 195:
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return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
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case 196:
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return aarch64_ext_sve_index (self, info, code, inst, errors);
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case 197:
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case 199:
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return aarch64_ext_sve_index (self, info, code, inst, errors);
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case 198:
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case 200:
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return aarch64_ext_sve_reglist (self, info, code, inst, errors);
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default: assert (0); abort ();
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}
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@ -218,6 +218,7 @@ const struct aarch64_operand aarch64_operands[] =
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{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an SVE vector register"},
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{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
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{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"},
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{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_11_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3}, "an indexed SVE vector register"},
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{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
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{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"},
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{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an indexed SVE vector register"},
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@ -294,6 +294,8 @@ const aarch64_field fields[] =
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{ 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
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{ 5, 1 }, /* SVE_i1: single-bit immediate. */
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{ 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
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{ 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
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{ 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */
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{ 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
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{ 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
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{ 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
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@ -1515,6 +1517,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
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{
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case AARCH64_OPND_SVE_Zm3_INDEX:
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case AARCH64_OPND_SVE_Zm3_22_INDEX:
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case AARCH64_OPND_SVE_Zm3_11_INDEX:
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case AARCH64_OPND_SVE_Zm4_INDEX:
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size = get_operand_fields_width (get_operand_from_code (type));
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shift = get_operand_specific_data (&aarch64_operands[type]);
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@ -3303,6 +3306,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
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case AARCH64_OPND_SVE_Zm3_INDEX:
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case AARCH64_OPND_SVE_Zm3_22_INDEX:
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case AARCH64_OPND_SVE_Zm3_11_INDEX:
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case AARCH64_OPND_SVE_Zm4_INDEX:
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case AARCH64_OPND_SVE_Zn_INDEX:
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snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
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@ -121,6 +121,8 @@ enum aarch64_field_kind
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FLD_SVE_Zt,
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FLD_SVE_i1,
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FLD_SVE_i3h,
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FLD_SVE_i3l,
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FLD_SVE_i3h2,
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FLD_SVE_imm3,
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FLD_SVE_imm4,
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FLD_SVE_imm5,
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@ -4960,6 +4960,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
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Y(SVE_REG, sve_quad_index, "SVE_Zm3_22_INDEX", \
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3 << OPD_F_OD_LSB, F(FLD_SVE_i3h, FLD_SVE_Zm_16), \
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"an indexed SVE vector register") \
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Y(SVE_REG, sve_quad_index, "SVE_Zm3_11_INDEX", \
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3 << OPD_F_OD_LSB, F(FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3), \
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"an indexed SVE vector register") \
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Y(SVE_REG, sve_quad_index, "SVE_Zm4_INDEX", \
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4 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \
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"an indexed SVE vector register") \
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