mirror of
https://github.com/espressif/binutils-gdb.git
synced 2025-06-21 10:34:21 +08:00
[binutils][aarch64] New SVE_Zm3_11_INDEX operand.
Introduce new operand SVE_Zm3_11_INDEX that indicates a register between z0-z7 stored in bits 18-16 and an index stored in bits 20-19:11. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_Zm3_11_INDEX. (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX. (fields): Handle SVE_i3l and SVE_i3h2 fields. * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2 fields. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
This commit is contained in:
@ -1,3 +1,8 @@
|
|||||||
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
||||||
|
|
||||||
|
* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX
|
||||||
|
operand.
|
||||||
|
|
||||||
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
||||||
|
|
||||||
* config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand.
|
* config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand.
|
||||||
|
@ -5637,6 +5637,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
|
|||||||
|
|
||||||
case AARCH64_OPND_SVE_Zm3_INDEX:
|
case AARCH64_OPND_SVE_Zm3_INDEX:
|
||||||
case AARCH64_OPND_SVE_Zm3_22_INDEX:
|
case AARCH64_OPND_SVE_Zm3_22_INDEX:
|
||||||
|
case AARCH64_OPND_SVE_Zm3_11_INDEX:
|
||||||
case AARCH64_OPND_SVE_Zm4_INDEX:
|
case AARCH64_OPND_SVE_Zm4_INDEX:
|
||||||
case AARCH64_OPND_SVE_Zn_INDEX:
|
case AARCH64_OPND_SVE_Zn_INDEX:
|
||||||
reg_type = REG_TYPE_ZN;
|
reg_type = REG_TYPE_ZN;
|
||||||
|
@ -1,3 +1,7 @@
|
|||||||
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
||||||
|
|
||||||
|
* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand.
|
||||||
|
|
||||||
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
||||||
|
|
||||||
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass.
|
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass.
|
||||||
|
@ -412,6 +412,7 @@ enum aarch64_opnd
|
|||||||
AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
|
AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
|
||||||
AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
|
AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
|
||||||
AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
|
AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
|
||||||
|
AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */
|
||||||
AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
|
AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
|
||||||
AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
|
AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
|
||||||
AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
|
AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
|
||||||
|
@ -1,3 +1,16 @@
|
|||||||
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
||||||
|
|
||||||
|
* aarch64-asm-2.c: Regenerated.
|
||||||
|
* aarch64-dis-2.c: Regenerated.
|
||||||
|
* aarch64-opc-2.c: Regenerated.
|
||||||
|
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
|
||||||
|
for SVE_Zm3_11_INDEX.
|
||||||
|
(aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
|
||||||
|
(fields): Handle SVE_i3l and SVE_i3h2 fields.
|
||||||
|
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
|
||||||
|
fields.
|
||||||
|
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
|
||||||
|
|
||||||
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
|
||||||
|
|
||||||
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
|
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
|
||||||
|
@ -647,8 +647,8 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||||||
case 189:
|
case 189:
|
||||||
case 190:
|
case 190:
|
||||||
case 191:
|
case 191:
|
||||||
case 195:
|
case 196:
|
||||||
case 198:
|
case 199:
|
||||||
return aarch64_ins_regno (self, info, code, inst, errors);
|
return aarch64_ins_regno (self, info, code, inst, errors);
|
||||||
case 14:
|
case 14:
|
||||||
return aarch64_ins_reg_extended (self, info, code, inst, errors);
|
return aarch64_ins_reg_extended (self, info, code, inst, errors);
|
||||||
@ -660,7 +660,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||||||
case 32:
|
case 32:
|
||||||
case 33:
|
case 33:
|
||||||
case 34:
|
case 34:
|
||||||
case 201:
|
case 202:
|
||||||
return aarch64_ins_reglane (self, info, code, inst, errors);
|
return aarch64_ins_reglane (self, info, code, inst, errors);
|
||||||
case 35:
|
case 35:
|
||||||
return aarch64_ins_reglist (self, info, code, inst, errors);
|
return aarch64_ins_reglist (self, info, code, inst, errors);
|
||||||
@ -704,7 +704,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||||||
case 180:
|
case 180:
|
||||||
case 181:
|
case 181:
|
||||||
case 182:
|
case 182:
|
||||||
case 200:
|
case 201:
|
||||||
return aarch64_ins_imm (self, info, code, inst, errors);
|
return aarch64_ins_imm (self, info, code, inst, errors);
|
||||||
case 43:
|
case 43:
|
||||||
case 44:
|
case 44:
|
||||||
@ -848,11 +848,12 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||||||
case 192:
|
case 192:
|
||||||
case 193:
|
case 193:
|
||||||
case 194:
|
case 194:
|
||||||
|
case 195:
|
||||||
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
|
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
|
||||||
case 196:
|
|
||||||
return aarch64_ins_sve_index (self, info, code, inst, errors);
|
|
||||||
case 197:
|
case 197:
|
||||||
case 199:
|
return aarch64_ins_sve_index (self, info, code, inst, errors);
|
||||||
|
case 198:
|
||||||
|
case 200:
|
||||||
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
|
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
|
||||||
default: assert (0); abort ();
|
default: assert (0); abort ();
|
||||||
}
|
}
|
||||||
|
@ -20078,8 +20078,8 @@ aarch64_extract_operand (const aarch64_operand *self,
|
|||||||
case 189:
|
case 189:
|
||||||
case 190:
|
case 190:
|
||||||
case 191:
|
case 191:
|
||||||
case 195:
|
case 196:
|
||||||
case 198:
|
case 199:
|
||||||
return aarch64_ext_regno (self, info, code, inst, errors);
|
return aarch64_ext_regno (self, info, code, inst, errors);
|
||||||
case 9:
|
case 9:
|
||||||
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
|
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
|
||||||
@ -20095,7 +20095,7 @@ aarch64_extract_operand (const aarch64_operand *self,
|
|||||||
case 32:
|
case 32:
|
||||||
case 33:
|
case 33:
|
||||||
case 34:
|
case 34:
|
||||||
case 201:
|
case 202:
|
||||||
return aarch64_ext_reglane (self, info, code, inst, errors);
|
return aarch64_ext_reglane (self, info, code, inst, errors);
|
||||||
case 35:
|
case 35:
|
||||||
return aarch64_ext_reglist (self, info, code, inst, errors);
|
return aarch64_ext_reglist (self, info, code, inst, errors);
|
||||||
@ -20140,7 +20140,7 @@ aarch64_extract_operand (const aarch64_operand *self,
|
|||||||
case 180:
|
case 180:
|
||||||
case 181:
|
case 181:
|
||||||
case 182:
|
case 182:
|
||||||
case 200:
|
case 201:
|
||||||
return aarch64_ext_imm (self, info, code, inst, errors);
|
return aarch64_ext_imm (self, info, code, inst, errors);
|
||||||
case 43:
|
case 43:
|
||||||
case 44:
|
case 44:
|
||||||
@ -20286,11 +20286,12 @@ aarch64_extract_operand (const aarch64_operand *self,
|
|||||||
case 192:
|
case 192:
|
||||||
case 193:
|
case 193:
|
||||||
case 194:
|
case 194:
|
||||||
|
case 195:
|
||||||
return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
|
return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
|
||||||
case 196:
|
|
||||||
return aarch64_ext_sve_index (self, info, code, inst, errors);
|
|
||||||
case 197:
|
case 197:
|
||||||
case 199:
|
return aarch64_ext_sve_index (self, info, code, inst, errors);
|
||||||
|
case 198:
|
||||||
|
case 200:
|
||||||
return aarch64_ext_sve_reglist (self, info, code, inst, errors);
|
return aarch64_ext_sve_reglist (self, info, code, inst, errors);
|
||||||
default: assert (0); abort ();
|
default: assert (0); abort ();
|
||||||
}
|
}
|
||||||
|
@ -218,6 +218,7 @@ const struct aarch64_operand aarch64_operands[] =
|
|||||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an SVE vector register"},
|
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an SVE vector register"},
|
||||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
|
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
|
||||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"},
|
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"},
|
||||||
|
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_11_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3}, "an indexed SVE vector register"},
|
||||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
|
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
|
||||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"},
|
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"},
|
||||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an indexed SVE vector register"},
|
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an indexed SVE vector register"},
|
||||||
|
@ -294,6 +294,8 @@ const aarch64_field fields[] =
|
|||||||
{ 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
|
{ 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
|
||||||
{ 5, 1 }, /* SVE_i1: single-bit immediate. */
|
{ 5, 1 }, /* SVE_i1: single-bit immediate. */
|
||||||
{ 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
|
{ 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
|
||||||
|
{ 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
|
||||||
|
{ 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */
|
||||||
{ 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
|
{ 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
|
||||||
{ 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
|
{ 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
|
||||||
{ 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
|
{ 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
|
||||||
@ -1515,6 +1517,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
|||||||
{
|
{
|
||||||
case AARCH64_OPND_SVE_Zm3_INDEX:
|
case AARCH64_OPND_SVE_Zm3_INDEX:
|
||||||
case AARCH64_OPND_SVE_Zm3_22_INDEX:
|
case AARCH64_OPND_SVE_Zm3_22_INDEX:
|
||||||
|
case AARCH64_OPND_SVE_Zm3_11_INDEX:
|
||||||
case AARCH64_OPND_SVE_Zm4_INDEX:
|
case AARCH64_OPND_SVE_Zm4_INDEX:
|
||||||
size = get_operand_fields_width (get_operand_from_code (type));
|
size = get_operand_fields_width (get_operand_from_code (type));
|
||||||
shift = get_operand_specific_data (&aarch64_operands[type]);
|
shift = get_operand_specific_data (&aarch64_operands[type]);
|
||||||
@ -3303,6 +3306,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
|||||||
|
|
||||||
case AARCH64_OPND_SVE_Zm3_INDEX:
|
case AARCH64_OPND_SVE_Zm3_INDEX:
|
||||||
case AARCH64_OPND_SVE_Zm3_22_INDEX:
|
case AARCH64_OPND_SVE_Zm3_22_INDEX:
|
||||||
|
case AARCH64_OPND_SVE_Zm3_11_INDEX:
|
||||||
case AARCH64_OPND_SVE_Zm4_INDEX:
|
case AARCH64_OPND_SVE_Zm4_INDEX:
|
||||||
case AARCH64_OPND_SVE_Zn_INDEX:
|
case AARCH64_OPND_SVE_Zn_INDEX:
|
||||||
snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
|
snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
|
||||||
|
@ -121,6 +121,8 @@ enum aarch64_field_kind
|
|||||||
FLD_SVE_Zt,
|
FLD_SVE_Zt,
|
||||||
FLD_SVE_i1,
|
FLD_SVE_i1,
|
||||||
FLD_SVE_i3h,
|
FLD_SVE_i3h,
|
||||||
|
FLD_SVE_i3l,
|
||||||
|
FLD_SVE_i3h2,
|
||||||
FLD_SVE_imm3,
|
FLD_SVE_imm3,
|
||||||
FLD_SVE_imm4,
|
FLD_SVE_imm4,
|
||||||
FLD_SVE_imm5,
|
FLD_SVE_imm5,
|
||||||
|
@ -4960,6 +4960,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
|||||||
Y(SVE_REG, sve_quad_index, "SVE_Zm3_22_INDEX", \
|
Y(SVE_REG, sve_quad_index, "SVE_Zm3_22_INDEX", \
|
||||||
3 << OPD_F_OD_LSB, F(FLD_SVE_i3h, FLD_SVE_Zm_16), \
|
3 << OPD_F_OD_LSB, F(FLD_SVE_i3h, FLD_SVE_Zm_16), \
|
||||||
"an indexed SVE vector register") \
|
"an indexed SVE vector register") \
|
||||||
|
Y(SVE_REG, sve_quad_index, "SVE_Zm3_11_INDEX", \
|
||||||
|
3 << OPD_F_OD_LSB, F(FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3), \
|
||||||
|
"an indexed SVE vector register") \
|
||||||
Y(SVE_REG, sve_quad_index, "SVE_Zm4_INDEX", \
|
Y(SVE_REG, sve_quad_index, "SVE_Zm4_INDEX", \
|
||||||
4 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \
|
4 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \
|
||||||
"an indexed SVE vector register") \
|
"an indexed SVE vector register") \
|
||||||
|
Reference in New Issue
Block a user