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[binutils][aarch64] New SVE_Zm3_11_INDEX operand.

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Introduce new operand SVE_Zm3_11_INDEX that indicates a register between
z0-z7 stored in bits 18-16 and an index stored in bits 20-19:11.

gas/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX
	operand.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
	for SVE_Zm3_11_INDEX.
	(aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
	(fields): Handle SVE_i3l and SVE_i3h2 fields.
	* aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
	fields.
	* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
This commit is contained in:
Matthew Malcomson
2019-05-09 10:29:17 +01:00
parent 3bd82c86f0
commit 116adc2747
11 changed files with 50 additions and 14 deletions
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1
include/opcode/aarch64.h
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@ -412,6 +412,7 @@ enum aarch64_opnd
AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */
AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */