Only perform access checks if 'check' is set.

Report unknown machine numbers.
Formatting tidy ups.

sim/arm/ChangeLog

@@ -1,5 +1,10 @@
 2002-05-27  Nick Clifton  <nickc@cambridge.redhat.com>
 
+	* armvirt.c (GetWord): Only perform access checks if 'check'
+	is set.
+	(PutWord): Likewise.
+	* wrapper.c (sim_create_inferior): Report unknown machine
+	numbers.
 	* thumbemu.c (ARMul_ThumbDecode, Case 31): Do not set LR to pc +
 	2, it has already been advanced.
 

sim/arm/armcopro.c

@@ -85,7 +85,6 @@ XScale_cp15_init (ARMul_State * state ATTRIBUTE_UNUSED)
 
   /* Initialise the ARM Control Register.  */
   XScale_cp15_opcode_2_is_0_Regs[1] = 0x00000078;
-
 }
 
 /* Check an access to a register.  */
@@ -253,7 +252,7 @@ write_cp15_reg (ARMul_State * state,
 	  value &= 0x00003b87;
 	  value |= 0x00000078;
 
-          /* Change the endianness if necessary */
+          /* Change the endianness if necessary.  */
           if ((value & ARMul_CP15_R1_ENDIAN) !=
 	      (XScale_cp15_opcode_2_is_0_Regs [reg] & ARMul_CP15_R1_ENDIAN))
 	    {
@@ -475,11 +474,11 @@ XScale_check_memacc (ARMul_State * state, ARMword * address, int store)
   /* Check for PID-ification.
      XXX BTB access support will require this test failing.  */
   r0 = (read_cp15_reg (13, 0, 0) & 0xfe000000);
-  if (r0 && (*address & 0xfe000000) == 0)
+  if (r0 && (* address & 0xfe000000) == 0)
-    *address |= r0;
+    * address |= r0;
 
   /* Check alignment fault enable/disable.  */
-  if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN) && (*address & 3))
+  if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN) && (* address & 3))
     ARMul_Abort (state, ARMul_DataAbortV);
 
   if (XScale_debug_moe (state, -1))
@@ -495,7 +494,7 @@ XScale_check_memacc (ARMul_State * state, ARMword * address, int store)
     {
       /* r1 is a inverse mask.  */
       if (e0 != 0 && ((store && e0 != 3) || (!store && e0 != 1))
-          && ((*address & ~r1) == (r0 & ~r1)))
+          && ((* address & ~r1) == (r0 & ~r1)))
 	{
           XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB);
           ARMul_OSHandleSWI (state, SWI_Breakpoint);
@@ -504,7 +503,7 @@ XScale_check_memacc (ARMul_State * state, ARMword * address, int store)
   else
     {
       if (e0 != 0 && ((store && e0 != 3) || (!store && e0 != 1))
-              && ((*address & ~3) == (r0 & ~3)))
+              && ((* address & ~3) == (r0 & ~3)))
 	{
           XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB);
           ARMul_OSHandleSWI (state, SWI_Breakpoint);
@@ -512,7 +511,7 @@ XScale_check_memacc (ARMul_State * state, ARMword * address, int store)
 
       e1 = (dbcon & ARMul_CP15_DBCON_E1) >> 2;
       if (e1 != 0 && ((store && e1 != 3) || (!store && e1 != 1))
-              && ((*address & ~3) == (r1 & ~3)))
+              && ((* address & ~3) == (r1 & ~3)))
 	{
           XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB);
           ARMul_OSHandleSWI (state, SWI_Breakpoint);
@@ -520,7 +519,7 @@ XScale_check_memacc (ARMul_State * state, ARMword * address, int store)
     }
 }
 
-/* Check set.  */
+/* Set the XScale FSR and FAR registers.  */
 
 void
 XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far)
@@ -847,7 +846,7 @@ write_cp14_reg (unsigned reg, ARMword value)
       /* Only BITS (27:12), BITS (10:8) and BITS (6:0) can be written.  */
       value &= 0x0ffff77f;
 
-      /* Reset the clock counter if necessary */
+      /* Reset the clock counter if necessary.  */
       if (value & ARMul_CP14_R0_CLKRST)
         XScale_cp14_Regs [1] = 0;
       break;

sim/arm/armemu.c

@@ -3206,7 +3206,7 @@ check_PMUintr:
 			ARMul_UndefInstr (state, instr);
 		      else
 			{
-			  /* XScale MAR insn.  Move two registers into accumulator.  */		      
+			  /* XScale MAR insn.  Move two registers into accumulator.  */
 			  state->Accumulator = state->Reg[BITS (12, 15)];
 			  state->Accumulator += (ARMdword) state->Reg[BITS (16, 19)] << 32;
 			}

sim/arm/armos.c

@@ -233,8 +233,8 @@ ARMul_OSInit (ARMul_State * state)
   /* Intel do not want DEMON SWI support.  */
    if (state->is_XScale)
     swi_mask = SWI_MASK_ANGEL;
- 
+
-  return TRUE;
+   return TRUE;
 }
 
 void

sim/arm/armsupp.c

@@ -138,6 +138,7 @@ void
 ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs)
 {
   state->Cpsr = ARMul_GetCPSR (state);
+
   if (state->Mode != USER26MODE
       && state->Mode != USER32MODE)
     {
@@ -569,7 +570,6 @@ ARMul_STC (ARMul_State * state, ARMword instr, ARMword address)
 #ifndef MODE32
   if (ADDREXCEPT (address) || VECTORACCESS (address))
     INTERNALABORT (address);
-
 #endif
   BUSUSEDINCPCN;
   if (BIT (21))

sim/arm/armvirt.c

@@ -64,7 +64,8 @@ GetWord (ARMul_State * state, ARMword address, int check)
   ARMword **pagetable;
   ARMword *pageptr;
 
-  XScale_check_memacc (state, &address, 0);
+  if (check)
+    XScale_check_memacc (state, &address, 0);
 
   page = address >> PAGEBITS;
   offset = (address & OFFSETBITS) >> 2;
@@ -99,7 +100,8 @@ PutWord (ARMul_State * state, ARMword address, ARMword data, int check)
   ARMword **pagetable;
   ARMword *pageptr;
 
-  XScale_check_memacc (state, &address, 1);
+  if (check)
+    XScale_check_memacc (state, &address, 1);
 
   page = address >> PAGEBITS;
   offset = (address & OFFSETBITS) >> 2;

sim/arm/wrapper.c

@@ -223,7 +223,8 @@ sim_create_inferior (sd, abfd, argv, env)
     default:
       (*sim_callback->printf_filtered)
 	(sim_callback,
-	 "Unknown machine type; please update sim_create_inferior.\n");
+	 "Unknown machine type '%d'; please update sim_create_inferior.\n",
+	 mach);
       /* fall through */
 
     case 0:
@@ -388,7 +389,7 @@ sim_store_register (sd, rn, memory, length)
   if (rn == 25)
     {
       state->Cpsr = frommem (state, memory);
-      ARMul_CPSRAltered (state);	     
+      ARMul_CPSRAltered (state);
     }
   else
     ARMul_SetReg (state, state->Mode, rn, frommem (state, memory));