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[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS

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This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.

This patch adds support for the mitigation for Spectre Variant 4 by
adding the PSTATE bit SSBS which are accessible using MSR and MRS
instructions. Although this is a mandatory addition to the ARMv8.5-A,
it is permitted to be added to any version of the ARMv8 architecture.
This is enabled using the command line option of +ssbs for older
versions.

*** include/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_SSBS): New.
	(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (operand_general_constraint_met_p): Add
	SSBS in the check for one-bit immediate.
	(aarch64_sys_regs): New entry for SSBS.
	(aarch64_sys_reg_supported_p): New check for above.
	(aarch64_pstatefields): New entry for SSBS.
	(aarch64_pstatefield_supported_p): New check for above.

*** gas/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (aarch64_features): Add new "ssbs".
	* doc/c-aarch64.texi: Document the same.
	* testsuite/gas/aarch64/ssbs-illegal1.d: New test.
	* testsuite/gas/aarch64/ssbs-illegal1.l: New test.
	* testsuite/gas/aarch64/ssbs-illegal2.d: New test.
	* testsuite/gas/aarch64/ssbs-illegal2.l: New test.
	* testsuite/gas/aarch64/ssbs.s: New test.
	* testsuite/gas/aarch64/ssbs1.d: Test with +ssbs
	* testsuite/gas/aarch64/ssbs2.d: Test with armv8.5-a.
This commit is contained in:
Sudakshina Das
2018-09-26 11:04:32 +01:00
committed by Richard Earnshaw
parent a97330e723
commit 104fefeebb
14 changed files with 252 additions and 1 deletions
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5
include/opcode/aarch64.h
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@ -82,6 +82,8 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL
/* ID_PFR2 instructions. */
#define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL
/* SSBS mechanism enabled. */
#define AARCH64_FEATURE_SSBS 0x800000000000ULL
/* Architectures are the sum of the base and extensions. */
@ -115,7 +117,8 @@ typedef uint32_t aarch64_insn;
| AARCH64_FEATURE_CVADP \
| AARCH64_FEATURE_BTI \
| AARCH64_FEATURE_SCXTNUM \
| AARCH64_FEATURE_ID_PFR2)
| AARCH64_FEATURE_ID_PFR2 \
| AARCH64_FEATURE_SSBS)
#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)