mirror of
https://github.com/espressif/binutils-gdb.git
synced 2025-06-22 02:50:08 +08:00
* interp.c (hash): Update to be more accurate.
(lookup_hash): Call hash rather than computing the hash
code here.
(do_format_1_2): Handle format 1 and format 2 instructions.
Get operands correctly and call the target function.
(do_format_6): Get operands correctly and call the target
function.
(do_formats_9_10): Rough cut so shift ops will work.
(sim_resume): Tweak to deal with format 1 and format 2
handling in a single funtion. Don't update the PC
for format 3 insns. Fix typos.
* simops.c: Slightly reorganize. Add condition code handling
to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
and "not" instructions.
* v850_sim.h (reg_t): Registers are 32bits.
(_state): The V850 has 32 general registers. Add a 32bit
psw and pc register too. Add accessor macros
Fixing lots of stuff. Starting to add condition code support. Basically
check pointing the work to date.
This commit is contained in:
Jeff Law
@ -1,5 +1,26 @@
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|||||||
Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com)
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Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com)
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* interp.c (hash): Update to be more accurate.
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(lookup_hash): Call hash rather than computing the hash
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code here.
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(do_format_1_2): Handle format 1 and format 2 instructions.
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Get operands correctly and call the target function.
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(do_format_6): Get operands correctly and call the target
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function.
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(do_formats_9_10): Rough cut so shift ops will work.
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(sim_resume): Tweak to deal with format 1 and format 2
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handling in a single funtion. Don't update the PC
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for format 3 insns. Fix typos.
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* simops.c: Slightly reorganize. Add condition code handling
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to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
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and "not" instructions.
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* v850_sim.h (reg_t): Registers are 32bits.
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(_state): The V850 has 32 general registers. Add a 32bit
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psw and pc register too. Add accessor macros
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* Makefile.in, interp.c, v850_sim.h: Bring over endianness
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changes from the d10v simulator.
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* simops.c: Add shift support.
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* simops.c: Add shift support.
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* simops.c: Add multiply & divide support. Abort for system
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* simops.c: Add multiply & divide support. Abort for system
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@ -56,7 +56,7 @@ INSTALL_XFORM1= $(INSTALL_XFORM) -b=.1
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AR = @AR@
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AR = @AR@
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AR_FLAGS = rc
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AR_FLAGS = rc
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CC = @CC@
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CC = @CC@
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CFLAGS = @CFLAGS@
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CFLAGS = @CFLAGS@ @DEFS@
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MAKEINFO = makeinfo
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MAKEINFO = makeinfo
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RANLIB = @RANLIB@
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RANLIB = @RANLIB@
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CC_FOR_BUILD = @CC_FOR_BUILD@
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CC_FOR_BUILD = @CC_FOR_BUILD@
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@ -28,12 +28,28 @@ static long
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hash(insn)
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hash(insn)
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long insn;
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long insn;
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{
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{
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/* XXX This isn't right for 32bit opcodes, hell it isn't even
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if ((insn & 0x30) == 0
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right for 16bit opcodes! */
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|| (insn & 0x38) == 0x10)
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if (insn & 0x0600)
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return (insn & 0x07e0) >> 5;
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return ((insn & 0x3F000000) >> 24);
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if ((insn & 0x3c) == 0x18
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else
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|| (insn & 0x3c) == 0x1c
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return((insn & 0x07E0) >> 5);
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|| (insn & 0x3c) == 0x20
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|| (insn & 0x3c) == 0x24
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|| (insn & 0x3c) == 0x28
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|| (insn & 0x3c) == 0x23)
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return (insn & 0x07c0) >> 6;
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if ((insn & 0x38) == 0x30)
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return (insn & 0x07e0) >> 5;
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/* What about sub-op field? XXX */
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if ((insn & 0x38) == 0x38)
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return (insn & 0x07e0) >> 5;
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if ((insn & 0x3e) == 0x3c)
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return (insn & 0x07c0) >> 6;
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if ((insn & 0x3f) == 0x3e)
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return (insn & 0xc7e0) >> 5;
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/* Not really correct. XXX */
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return insn & 0xffffffff;
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}
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}
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static struct hash_entry *
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static struct hash_entry *
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@ -42,10 +58,7 @@ lookup_hash (ins)
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{
|
{
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struct hash_entry *h;
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struct hash_entry *h;
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if (ins & 0x0f00)
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h = &hash_table[hash(ins)];
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h = &hash_table[(ins & 0x3F000000) >> 24];
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else
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h = &hash_table[(ins & 0x07E0) >> 5];
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while ( (ins & h->mask) != h->opcode)
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while ( (ins & h->mask) != h->opcode)
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{
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{
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@ -60,56 +73,108 @@ lookup_hash (ins)
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}
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}
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uint32
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uint32
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get_longword_swap (x)
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get_longword (x)
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uint16 x;
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uint8 *x;
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{
|
{
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uint8 *a = (uint8 *)(x + State.imem);
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uint8 *a = x;
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return (a[0]<<24) + (a[1]<<16) + (a[2]<<8) + (a[3]);
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return (a[3]<<24) + (a[2]<<16) + (a[1]<<8) + (a[0]);
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|
}
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|
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int64
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get_longlong (x)
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uint8 *x;
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{
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uint8 *a = x;
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return ((int64)a[0]<<56) + ((int64)a[1]<<48) + ((int64)a[2]<<40) + ((int64)a[3]<<32) +
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((int64)a[4]<< 24) + ((int64)a[5]<<16) + ((int64)a[6]<<8) + (int64)a[7];
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}
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}
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uint16
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uint16
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get_word_swap (x)
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get_word (x)
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uint16 x;
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uint8 *x;
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{
|
{
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uint8 *a = (uint8 *)(x + State.imem);
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uint8 *a = x;
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return (a[0]<<8) + a[1];
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return ((uint16)a[0]<<8) + a[1];
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}
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}
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|
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|
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void
|
void
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write_word_swap (addr, data)
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write_word (addr, data)
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uint16 addr, data;
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uint8 *addr;
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|
uint16 data;
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{
|
{
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uint8 *a = (uint8 *)(addr + State.imem);
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uint8 *a = addr;
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a[0] = data >> 8;
|
a[0] = data >> 8;
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a[1] = data & 0xff;
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a[1] = data & 0xff;
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}
|
}
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static void
|
void
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do_format_1 (insn)
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write_longword (addr, data)
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uint32 insn;
|
uint8 *addr;
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|
uint32 data;
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{
|
{
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printf("format 1 0x%x\n", insn >> 16);
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addr[0] = (data >> 24) & 0xff;
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addr[1] = (data >> 16) & 0xff;
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addr[2] = (data >> 8) & 0xff;
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addr[3] = data & 0xff;
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|
}
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|
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|
void
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|
write_longlong (addr, data)
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|
uint8 *addr;
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|
int64 data;
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|
{
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|
uint8 *a = addr;
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a[0] = data >> 56;
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a[1] = (data >> 48) & 0xff;
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a[2] = (data >> 40) & 0xff;
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a[3] = (data >> 32) & 0xff;
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a[4] = (data >> 24) & 0xff;
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a[5] = (data >> 16) & 0xff;
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a[6] = (data >> 8) & 0xff;
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|
a[7] = data & 0xff;
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}
|
}
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|
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||||||
static void
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static void
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do_format_2 (insn)
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get_operands (struct simops *s, uint32 ins)
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|
{
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int i, shift, bits, flags;
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uint32 mask;
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for (i=0; i < s->numops; i++)
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{
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shift = s->operands[3*i];
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bits = s->operands[3*i+1];
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flags = s->operands[3*i+2];
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mask = 0x7FFFFFFF >> (31 - bits);
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OP[i] = (ins >> shift) & mask;
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|
}
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}
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static void
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|
do_format_1_2 (insn)
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uint32 insn;
|
uint32 insn;
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{
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{
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printf("format 2 0x%x\n", insn >> 16);
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struct hash_entry *h;
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printf("format 1 or 2 0x%x\n", insn);
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h = lookup_hash (insn);
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OP[0] = insn & 0x1f;
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OP[1] = (insn >> 11) & 0x1f;
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(h->ops->func) ();
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}
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}
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static void
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static void
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do_format_3 (insn)
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do_format_3 (insn)
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uint32 insn;
|
uint32 insn;
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{
|
{
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printf("format 3 0x%x\n", insn >> 16);
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printf("format 3 0x%x\n", insn);
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}
|
}
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|
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||||||
static void
|
static void
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do_format_4 (insn)
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do_format_4 (insn)
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uint32 insn;
|
uint32 insn;
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{
|
{
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printf("format 4 0x%x\n", insn >> 16);
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printf("format 4 0x%x\n", insn);
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}
|
}
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||||||
|
|
||||||
static void
|
static void
|
||||||
@ -123,7 +188,14 @@ static void
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|||||||
do_format_6 (insn)
|
do_format_6 (insn)
|
||||||
uint32 insn;
|
uint32 insn;
|
||||||
{
|
{
|
||||||
|
struct hash_entry *h;
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printf("format 6 0x%x\n", insn);
|
printf("format 6 0x%x\n", insn);
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|
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|
h = lookup_hash (insn);
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|
OP[0] = (insn >> 16) & 0xffff;
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|
OP[1] = insn & 0x1f;
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|
OP[2] = (insn >> 11) & 0x1f;
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||||||
|
(h->ops->func) ();
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}
|
}
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||||||
|
|
||||||
static void
|
static void
|
||||||
@ -144,7 +216,13 @@ static void
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|||||||
do_formats_9_10 (insn)
|
do_formats_9_10 (insn)
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uint32 insn;
|
uint32 insn;
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{
|
{
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||||||
|
struct hash_entry *h;
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printf("formats 9 and 10 0x%x\n", insn);
|
printf("formats 9 and 10 0x%x\n", insn);
|
||||||
|
|
||||||
|
h = lookup_hash (insn);
|
||||||
|
OP[0] = insn & 0x1f;
|
||||||
|
OP[1] = (insn >> 11) & 0x1f;
|
||||||
|
(h->ops->func) ();
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
@ -263,15 +341,11 @@ sim_resume (step, siggnal)
|
|||||||
{
|
{
|
||||||
inst = RLW (PC);
|
inst = RLW (PC);
|
||||||
oldpc = PC;
|
oldpc = PC;
|
||||||
opcode = (inst & 0x07e00000) >> 21;
|
opcode = (inst & 0x07e0) >> 5;
|
||||||
if ((opcode & 0x30) == 0)
|
if ((opcode & 0x30) == 0
|
||||||
|
|| (opcode & 0x38) == 0x10)
|
||||||
{
|
{
|
||||||
do_format_1 (inst >> 16);
|
do_format_1_2 (inst & 0xffff);
|
||||||
PC += 2;
|
|
||||||
}
|
|
||||||
else if ((opcode & 0x38) == 0x10)
|
|
||||||
{
|
|
||||||
do_format_2 (inst >> 16);
|
|
||||||
PC += 2;
|
PC += 2;
|
||||||
}
|
}
|
||||||
else if ((opcode & 0x3C) == 0x18
|
else if ((opcode & 0x3C) == 0x18
|
||||||
@ -280,13 +354,13 @@ sim_resume (step, siggnal)
|
|||||||
|| (opcode & 0x3C) == 0x24
|
|| (opcode & 0x3C) == 0x24
|
||||||
|| (opcode & 0x3C) == 0x28)
|
|| (opcode & 0x3C) == 0x28)
|
||||||
{
|
{
|
||||||
do_format_4 (inst >> 16);
|
do_format_4 (inst & 0xffff);
|
||||||
PC += 2;
|
PC += 2;
|
||||||
}
|
}
|
||||||
else if ((opcode& 0x3C) == 0x23)
|
else if ((opcode & 0x3C) == 0x23)
|
||||||
{
|
{
|
||||||
do_format_3 (inst >> 16);
|
do_format_3 (inst & 0xffff);
|
||||||
PC += 2;
|
/* No PC update, it's done in the instruction. */
|
||||||
}
|
}
|
||||||
else if ((opcode & 0x38) == 0x30)
|
else if ((opcode & 0x38) == 0x30)
|
||||||
{
|
{
|
||||||
@ -303,7 +377,7 @@ sim_resume (step, siggnal)
|
|||||||
do_format_5 (inst);
|
do_format_5 (inst);
|
||||||
PC += 4;
|
PC += 4;
|
||||||
}
|
}
|
||||||
else if ((opcode & 0x3E) == 0x3C)
|
else if ((opcode & 0x3F) == 0x3E)
|
||||||
{
|
{
|
||||||
do_format_8 (inst);
|
do_format_8 (inst);
|
||||||
PC += 4;
|
PC += 4;
|
||||||
|
|||||||
@ -123,39 +123,85 @@ OP_660 ()
|
|||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/* add reg, reg
|
/* add reg, reg */
|
||||||
|
|
||||||
XXX condition codes. */
|
|
||||||
void
|
void
|
||||||
OP_1C0 ()
|
OP_1C0 ()
|
||||||
{
|
{
|
||||||
State.regs[OP[1]] += State.regs[OP[0]];
|
unsigned int op0, op1, result, z, s, cy, ov;
|
||||||
|
|
||||||
|
/* Compute the result. */
|
||||||
|
op0 = State.regs[OP[0]];
|
||||||
|
op1 = State.regs[OP[1]];
|
||||||
|
result = op0 + op1;
|
||||||
|
|
||||||
|
/* Compute the condition codes. */
|
||||||
|
z = (result == 0);
|
||||||
|
s = (result & 0x80000000);
|
||||||
|
cy = (result < op0 || result < op1);
|
||||||
|
ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
|
||||||
|
&& (op0 & 0x80000000) != (result & 0x80000000));
|
||||||
|
|
||||||
|
/* Store the result and condition codes. */
|
||||||
|
State.regs[OP[1]] = result;
|
||||||
|
State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
||||||
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
||||||
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
|
||||||
}
|
}
|
||||||
|
|
||||||
/* add sign_extend(imm5), reg
|
/* add sign_extend(imm5), reg */
|
||||||
|
|
||||||
XXX condition codes. */
|
|
||||||
void
|
void
|
||||||
OP_240 ()
|
OP_240 ()
|
||||||
{
|
{
|
||||||
int value = OP[0];
|
unsigned int op0, op1, result, z, s, cy, ov;
|
||||||
|
int temp;
|
||||||
|
|
||||||
value = (value << 27) >> 27;
|
/* Compute the result. */
|
||||||
|
temp = (OP[0] & 0x1f);
|
||||||
|
temp = (temp << 27) >> 27;
|
||||||
|
op0 = temp;
|
||||||
|
op1 = State.regs[OP[1]];
|
||||||
|
result = op0 + op1;
|
||||||
|
|
||||||
State.regs[OP[1]] += value;
|
/* Compute the condition codes. */
|
||||||
|
z = (result == 0);
|
||||||
|
s = (result & 0x80000000);
|
||||||
|
cy = (result < op0 || result < op1);
|
||||||
|
ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
|
||||||
|
&& (op0 & 0x80000000) != (result & 0x80000000));
|
||||||
|
|
||||||
|
/* Store the result and condition codes. */
|
||||||
|
State.regs[OP[1]] = result;
|
||||||
|
State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
||||||
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
||||||
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
|
||||||
}
|
}
|
||||||
|
|
||||||
/* addi sign_extend(imm16), reg, reg
|
/* addi sign_extend(imm16), reg, reg */
|
||||||
|
|
||||||
XXX condition codes. */
|
|
||||||
void
|
void
|
||||||
OP_600 ()
|
OP_600 ()
|
||||||
{
|
{
|
||||||
int value = OP[0];
|
unsigned int op0, op1, result, z, s, cy, ov;
|
||||||
|
int temp;
|
||||||
|
|
||||||
value = (value << 16) >> 16;
|
/* Compute the result. */
|
||||||
|
temp = (OP[0] & 0xffff);
|
||||||
|
temp = (temp << 16) >> 16;
|
||||||
|
op0 = temp;
|
||||||
|
op1 = State.regs[OP[1]];
|
||||||
|
result = op0 + op1;
|
||||||
|
|
||||||
State.regs[OP[2]] = State.regs[OP[1]] + value;
|
/* Compute the condition codes. */
|
||||||
|
z = (result == 0);
|
||||||
|
s = (result & 0x80000000);
|
||||||
|
cy = (result < op0 || result < op1);
|
||||||
|
ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
|
||||||
|
&& (op0 & 0x80000000) != (result & 0x80000000));
|
||||||
|
|
||||||
|
/* Store the result and condition codes. */
|
||||||
|
State.regs[OP[2]] = result;
|
||||||
|
State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
||||||
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
||||||
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
|
||||||
}
|
}
|
||||||
|
|
||||||
/* sub reg1, reg2
|
/* sub reg1, reg2
|
||||||
@ -327,15 +373,6 @@ OP_80 ()
|
|||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
/* not reg1, reg2
|
|
||||||
|
|
||||||
XXX condition codes */
|
|
||||||
void
|
|
||||||
OP_20 ()
|
|
||||||
{
|
|
||||||
State.regs[OP[1]] = ~State.regs[OP[0]];
|
|
||||||
}
|
|
||||||
|
|
||||||
/* sar zero_extend(imm5),reg1
|
/* sar zero_extend(imm5),reg1
|
||||||
|
|
||||||
XXX condition codes. */
|
XXX condition codes. */
|
||||||
@ -413,70 +450,148 @@ OP_7E0 ()
|
|||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
/* or reg, reg
|
/* or reg, reg */
|
||||||
|
|
||||||
XXX condition codes. */
|
|
||||||
void
|
void
|
||||||
OP_100 ()
|
OP_100 ()
|
||||||
{
|
{
|
||||||
State.regs[OP[1]] |= State.regs[OP[0]];
|
unsigned int op0, op1, result, z, s, cy, ov;
|
||||||
|
|
||||||
|
/* Compute the result. */
|
||||||
|
op0 = State.regs[OP[0]];
|
||||||
|
op1 = State.regs[OP[1]];
|
||||||
|
result = op0 | op1;
|
||||||
|
|
||||||
|
/* Compute the condition codes. */
|
||||||
|
z = (result == 0);
|
||||||
|
s = (result & 0x80000000);
|
||||||
|
|
||||||
|
/* Store the result and condition codes. */
|
||||||
|
State.regs[OP[1]] = result;
|
||||||
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
|
||||||
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ori zero_extend(imm16), reg, reg
|
/* ori zero_extend(imm16), reg, reg */
|
||||||
|
|
||||||
XXX condition codes */
|
|
||||||
void
|
void
|
||||||
OP_680 ()
|
OP_680 ()
|
||||||
{
|
{
|
||||||
int value = OP[0];
|
unsigned int op0, op1, result, z, s, cy, ov;
|
||||||
|
|
||||||
value &= 0xffff;
|
op0 = OP[0] & 0xffff;
|
||||||
|
op1 = State.regs[OP[1]];
|
||||||
|
result = op0 | op1;
|
||||||
|
|
||||||
State.regs[OP[2]] = State.regs[OP[1]] | value;
|
/* Compute the condition codes. */
|
||||||
|
z = (result == 0);
|
||||||
|
s = (result & 0x80000000);
|
||||||
|
|
||||||
|
/* Store the result and condition codes. */
|
||||||
|
State.regs[OP[2]] = result;
|
||||||
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
|
||||||
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
||||||
|
State.psw |= (z ? PSW_Z : 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* and reg, reg
|
/* and reg, reg */
|
||||||
|
|
||||||
XXX condition codes. */
|
|
||||||
void
|
void
|
||||||
OP_140 ()
|
OP_140 ()
|
||||||
{
|
{
|
||||||
State.regs[OP[1]] &= State.regs[OP[0]];
|
unsigned int op0, op1, result, z, s, cy, ov;
|
||||||
|
|
||||||
|
/* Compute the result. */
|
||||||
|
op0 = State.regs[OP[0]];
|
||||||
|
op1 = State.regs[OP[1]];
|
||||||
|
result = op0 & op1;
|
||||||
|
|
||||||
|
/* Compute the condition codes. */
|
||||||
|
z = (result == 0);
|
||||||
|
s = (result & 0x80000000);
|
||||||
|
|
||||||
|
/* Store the result and condition codes. */
|
||||||
|
State.regs[OP[1]] = result;
|
||||||
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
|
||||||
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
||||||
}
|
}
|
||||||
|
|
||||||
/* andi zero_extend(imm16), reg, reg
|
/* andi zero_extend(imm16), reg, reg */
|
||||||
|
|
||||||
XXX condition codes. */
|
|
||||||
void
|
void
|
||||||
OP_6C0 ()
|
OP_6C0 ()
|
||||||
{
|
{
|
||||||
int value = OP[0];
|
unsigned int op0, op1, result, z, s, cy, ov;
|
||||||
|
|
||||||
value &= 0xffff;
|
op0 = OP[0] & 0xffff;
|
||||||
|
op1 = State.regs[OP[1]];
|
||||||
|
result = op0 & op1;
|
||||||
|
|
||||||
State.regs[OP[2]] = State.regs[OP[1]] & value;
|
/* Compute the condition codes. */
|
||||||
|
z = (result == 0);
|
||||||
|
|
||||||
|
/* Store the result and condition codes. */
|
||||||
|
State.regs[OP[2]] = result;
|
||||||
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
|
||||||
|
State.psw |= (z ? PSW_Z : 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* xor reg, reg
|
/* xor reg, reg */
|
||||||
|
|
||||||
XXX condition codes. */
|
|
||||||
void
|
void
|
||||||
OP_120 ()
|
OP_120 ()
|
||||||
{
|
{
|
||||||
State.regs[OP[1]] ^= State.regs[OP[0]];
|
unsigned int op0, op1, result, z, s, cy, ov;
|
||||||
|
|
||||||
|
/* Compute the result. */
|
||||||
|
op0 = State.regs[OP[0]];
|
||||||
|
op1 = State.regs[OP[1]];
|
||||||
|
result = op0 ^ op1;
|
||||||
|
|
||||||
|
/* Compute the condition codes. */
|
||||||
|
z = (result == 0);
|
||||||
|
s = (result & 0x80000000);
|
||||||
|
|
||||||
|
/* Store the result and condition codes. */
|
||||||
|
State.regs[OP[1]] = result;
|
||||||
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
|
||||||
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
||||||
}
|
}
|
||||||
|
|
||||||
/* xori zero_extend(imm16), reg, reg
|
/* xori zero_extend(imm16), reg, reg */
|
||||||
|
|
||||||
XXX condition codes. */
|
|
||||||
void
|
void
|
||||||
OP_6A0 ()
|
OP_6A0 ()
|
||||||
{
|
{
|
||||||
int value = OP[0];
|
unsigned int op0, op1, result, z, s, cy, ov;
|
||||||
|
|
||||||
value &= 0xffff;
|
op0 = OP[0] & 0xffff;
|
||||||
|
op1 = State.regs[OP[1]];
|
||||||
|
result = op0 ^ op1;
|
||||||
|
|
||||||
State.regs[OP[2]] = State.regs[OP[1]] ^ value;
|
/* Compute the condition codes. */
|
||||||
|
z = (result == 0);
|
||||||
|
s = (result & 0x80000000);
|
||||||
|
|
||||||
|
/* Store the result and condition codes. */
|
||||||
|
State.regs[OP[2]] = result;
|
||||||
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
|
||||||
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
||||||
|
State.psw |= (z ? PSW_Z : 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* not reg1, reg2 */
|
||||||
|
void
|
||||||
|
OP_20 ()
|
||||||
|
{
|
||||||
|
unsigned int op0, result, z, s, cy, ov;
|
||||||
|
|
||||||
|
/* Compute the result. */
|
||||||
|
op0 = State.regs[OP[0]];
|
||||||
|
result = ~op0;
|
||||||
|
|
||||||
|
/* Compute the condition codes. */
|
||||||
|
z = (result == 0);
|
||||||
|
s = (result & 0x80000000);
|
||||||
|
|
||||||
|
/* Store the result and condition codes. */
|
||||||
|
State.regs[OP[1]] = result;
|
||||||
|
State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
|
||||||
|
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
|||||||
@ -13,7 +13,7 @@ typedef signed int int32;
|
|||||||
typedef signed long long int64;
|
typedef signed long long int64;
|
||||||
|
|
||||||
/* FIXME: V850 defines */
|
/* FIXME: V850 defines */
|
||||||
typedef uint16 reg_t;
|
typedef uint32 reg_t;
|
||||||
|
|
||||||
struct simops
|
struct simops
|
||||||
{
|
{
|
||||||
@ -26,21 +26,9 @@ struct simops
|
|||||||
|
|
||||||
struct _state
|
struct _state
|
||||||
{
|
{
|
||||||
reg_t regs[16]; /* general-purpose registers */
|
reg_t regs[32]; /* general-purpose registers */
|
||||||
reg_t cregs[16]; /* control registers */
|
reg_t pc;
|
||||||
int64 a[2]; /* accumulators */
|
reg_t psw;
|
||||||
uint8 SM;
|
|
||||||
uint8 EA;
|
|
||||||
uint8 DB;
|
|
||||||
uint8 IE;
|
|
||||||
uint8 RP;
|
|
||||||
uint8 MD;
|
|
||||||
uint8 FX;
|
|
||||||
uint8 ST;
|
|
||||||
uint8 F0;
|
|
||||||
uint8 F1;
|
|
||||||
uint8 C;
|
|
||||||
uint8 exe;
|
|
||||||
uint8 *imem;
|
uint8 *imem;
|
||||||
uint8 *dmem;
|
uint8 *dmem;
|
||||||
int exception;
|
int exception;
|
||||||
@ -49,16 +37,17 @@ struct _state
|
|||||||
extern uint16 OP[4];
|
extern uint16 OP[4];
|
||||||
extern struct simops Simops[];
|
extern struct simops Simops[];
|
||||||
|
|
||||||
#define PC (State.cregs[2])
|
#define PC (State.pc)
|
||||||
#define PSW (State.cregs[0])
|
#define PSW (State.psw)
|
||||||
#define BPSW (State.cregs[1])
|
|
||||||
#define BPC (State.cregs[3])
|
#define PSW_NP 0x80
|
||||||
#define RPT_C (State.cregs[7])
|
#define PSW_EP 0x40
|
||||||
#define RPT_S (State.cregs[8])
|
#define PSW_ID 0x20
|
||||||
#define RPT_E (State.cregs[9])
|
#define PSW_SAT 0x10
|
||||||
#define MOD_S (State.cregs[10])
|
#define PSW_CY 0x8
|
||||||
#define MOD_E (State.cregs[11])
|
#define PSW_OV 0x4
|
||||||
#define IBA (State.cregs[14])
|
#define PSW_S 0x2
|
||||||
|
#define PSW_Z 0x1
|
||||||
|
|
||||||
#define SEXT3(x) ((((x)&0x7)^(~3))+4)
|
#define SEXT3(x) ((((x)&0x7)^(~3))+4)
|
||||||
|
|
||||||
@ -95,17 +84,28 @@ extern struct simops Simops[];
|
|||||||
|
|
||||||
#ifdef WORDS_BIGENDIAN
|
#ifdef WORDS_BIGENDIAN
|
||||||
|
|
||||||
#define RW(x) (*((uint16 *)((x)+State.imem)))
|
#define RW(x) (*((uint16 *)((x)+State.imem)))
|
||||||
#define RLW(x) (*((uint32 *)((x)+State.imem)))
|
#define RLW(x) (*((uint32 *)((x)+State.imem)))
|
||||||
#define SW(addr,data) RW(addr)=data
|
#define SW(addr,data) RW(addr)=data
|
||||||
|
#define READ_16(x) (*((int16 *)(x)))
|
||||||
|
#define WRITE_16(addr,data) (*(int16 *)(addr)=data)
|
||||||
|
#define READ_64(x) (*((int64 *)(x)))
|
||||||
|
#define WRITE_64(addr,data) (*(int64 *)(addr)=data)
|
||||||
|
|
||||||
#else
|
#else
|
||||||
|
|
||||||
uint32 get_longword_swap PARAMS ((uint16 x));
|
uint32 get_longword PARAMS ((uint8 *));
|
||||||
uint16 get_word_swap PARAMS ((uint16 x));
|
uint16 get_word PARAMS ((uint8 *));
|
||||||
void write_word_swap PARAMS ((uint16 addr, uint16 data));
|
int64 get_longlong PARAMS ((uint8 *));
|
||||||
#define SW(addr,data) write_word_swap(addr,data)
|
void write_word PARAMS ((uint8 *addr, uint16 data));
|
||||||
#define RW(x) get_word_swap(x)
|
void write_longlong PARAMS ((uint8 *addr, int64 data));
|
||||||
#define RLW(x) get_longword_swap(x)
|
|
||||||
|
#define SW(addr,data) write_word((long)(addr)+State.imem,data)
|
||||||
|
#define RW(x) get_word((long)(x)+State.imem)
|
||||||
|
#define RLW(x) get_longword((long)(x)+State.imem)
|
||||||
|
#define READ_16(x) get_word(x)
|
||||||
|
#define WRITE_16(addr,data) write_word(addr,data)
|
||||||
|
#define READ_64(x) get_longlong(x)
|
||||||
|
#define WRITE_64(addr,data) write_longlong(addr,data)
|
||||||
|
|
||||||
#endif /* not WORDS_BIGENDIAN */
|
#endif /* not WORDS_BIGENDIAN */
|
||||||
|
|||||||
Reference in New Issue
Block a user