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gas: blackfin: gas: blackfin: reject invalid BYTEOP16P insns
The destination registers must be different with BYTEOP16P insns, otherwise the hardware throws up an exception. So reject them. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
@ -1,3 +1,8 @@
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2011-03-29 Mike Frysinger <vapier@gentoo.org>
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* config/bfin-parse.y (BYTEOP16P): Return yyerror when dest
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reg $2 is the same as dest reg $4.
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2011-03-28 Mike Frysinger <vapier@gentoo.org>
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2011-03-28 Mike Frysinger <vapier@gentoo.org>
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* config/bfin-parse.y (16bit acc add): Return yyerror when dest
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* config/bfin-parse.y (16bit acc add): Return yyerror when dest
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@ -831,6 +831,8 @@ asm_1:
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{
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{
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if (!IS_DREG ($2) || !IS_DREG ($4))
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if (!IS_DREG ($2) || !IS_DREG ($4))
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return yyerror ("Dregs expected");
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return yyerror ("Dregs expected");
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else if (REG_SAME ($2, $4))
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return yyerror ("Illegal dest register combination");
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else if (!valid_dreg_pair (&$9, $11))
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else if (!valid_dreg_pair (&$9, $11))
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return yyerror ("Bad dreg pair");
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return yyerror ("Bad dreg pair");
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else if (!valid_dreg_pair (&$13, $15))
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else if (!valid_dreg_pair (&$13, $15))
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@ -1,3 +1,8 @@
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2011-03-29 Mike Frysinger <vapier@gentoo.org>
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* gas/bfin/expected_errors.s: Add invalid BYTEOP16P insn tests.
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* gas/bfin/expected_errors.l: Add new error messages.
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2011-03-28 Mike Frysinger <vapier@gentoo.org>
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2011-03-28 Mike Frysinger <vapier@gentoo.org>
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* gas/bfin/expected_errors.s: Add invalid 16bit acc add insn tests.
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* gas/bfin/expected_errors.s: Add invalid 16bit acc add insn tests.
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@ -101,3 +101,5 @@
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.*:127: Error: Differing source registers.
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.*:127: Error: Differing source registers.
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.*:129: Error: Register mismatch.
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.*:129: Error: Register mismatch.
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.*:131: Error: Illegal dest register combination. Input text was A0.H.
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.*:131: Error: Illegal dest register combination. Input text was A0.H.
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.*:133: Error: Illegal dest register combination.
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.*:134: Error: Illegal dest register combination.
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@ -129,3 +129,6 @@
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R0 = R3 + R4, R1 = R5 - R6;
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R0 = R3 + R4, R1 = R5 - R6;
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R7 = A1.L + A1.H, R7 = A0.L + A0.H;
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R7 = A1.L + A1.H, R7 = A0.L + A0.H;
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(R0, R0) = BYTEOP16P (R1:0, R3:2);
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(R7, R7) = BYTEOP16P (R1:0, R3:2);
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