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* v850-opc.c (v850_opcodes): Fix order of displacement

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and register for "set1", "clr1", "not1", and "tst1".
This commit is contained in:
Jeff Law
1996-08-22 07:06:13 +00:00
parent 088d5b7309
commit 0bdf3144c6
2 changed files with 9 additions and 4 deletions
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5
opcodes/ChangeLog
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@ -1,4 +1,9 @@
start-sanitize-v850 start-sanitize-v850
Thu Aug 22 01:05:24 1996 Jeffrey A Law (law@cygnus.com)
* v850-opc.c (v850_opcodes): Fix order of displacement
and register for "set1", "clr1", "not1", and "tst1".
Wed Aug 21 18:46:26 1996 Jeffrey A Law (law@cygnus.com) Wed Aug 21 18:46:26 1996 Jeffrey A Law (law@cygnus.com)
* v850-opc.c (v850_operands): Add "B3" support. * v850-opc.c (v850_operands): Add "B3" support.

8
opcodes/v850-opc.c
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@ -193,10 +193,10 @@ const struct v850_opcode v850_opcodes[] = {
{ "jr", one(0x0780), one(0xffe0), { D22 } }, { "jr", one(0x0780), one(0xffe0), { D22 } },
/* bit manipulation instructions */ /* bit manipulation instructions */
{ "set1", two(0x07c0,0x0000), two(0xc7e0,0x0000), {B3, R1, D16} }, { "set1", two(0x07c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
{ "not1", two(0x47c0,0x0000), two(0xc7e0,0x0000), {B3, R1, D16} }, { "not1", two(0x47c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
{ "clr1", two(0x87c0,0x0000), two(0xc7e0,0x0000), {B3, R1, D16} }, { "clr1", two(0x87c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
{ "tst1", two(0xc7c0,0x0000), two(0xc7e0,0x0000), {B3, R1, D16} }, { "tst1", two(0xc7c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
/* special instructions */ /* special instructions */
{ "di", two(0x07e0,0x0160), two(0xffff,0xffff), {0} }, { "di", two(0x07e0,0x0160), two(0xffff,0xffff), {0} },