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AArch64: add GAS support for UDF instruction

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binutils * testsuite/binutils-all/aarch64/in-order-all.d: Update to use new
          disassembly.
        * testsuite/binutils-all/aarch64/out-of-order-all.d: Likewise.

ld/     * testsuite/ld-aarch64/erratum843419_tls_ie.d: Use udf in disassembly.
        * testsuite/ld-aarch64/farcall-b-section.d: Likewise.
        * testsuite/ld-aarch64/farcall-back.d: Likewise.
        * testsuite/ld-aarch64/farcall-bl-section.d: Likewise.

gas/   * config/tc-aarch64.c (fix_insn): Implement for AARCH64_OPND_UNDEFINED.
          (parse_operands): Implement for AARCH64_OPND_UNDEFINED.
        * testsuite/gas/aarch64/udf.s: New.
        * testsuite/gas/aarch64/udf.d: New.
        * testsuite/gas/aarch64/udf-invalid.s: New.
        * testsuite/gas/aarch64/udf-invalid.l: New.
        * testsuite/gas/aarch64/udf-invalid.d: New.

include * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_UNDEFINED.

opcodes * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
        * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
          (operand_general_constraint_met_p): validate AARCH64_OPND_UNDEFINED.
        * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry for
          FLD_imm16_2.
        * aarch64-asm-2.c: Regenerated.
        * aarch64-dis-2.c: Regenerated.
        * aarch64-opc-2.c: Regenerated.
This commit is contained in:
Alex Coplan
2020-04-30 15:47:30 +01:00
committed by Nick Clifton
parent 8a8a117123
commit 09c1e68a16
25 changed files with 2620 additions and 2497 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
binutils/ChangeLog
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@ -1,3 +1,9 @@
2020-04-30 Alex Coplan <alex.coplan@arm.com>
* testsuite/binutils-all/aarch64/in-order-all.d: Update to use new
disassembly.
* testsuite/binutils-all/aarch64/out-of-order-all.d: Likewise.
2020-04-30 Nick Clifton <nickc@redhat.com> 2020-04-30 Nick Clifton <nickc@redhat.com>
* testsuite/lib/binutils-common.exp (check_pie_support): New * testsuite/lib/binutils-common.exp (check_pie_support): New

6
binutils/testsuite/binutils-all/aarch64/in-order-all.d
View File

@ -10,7 +10,7 @@ Disassembly of section \.func1:
.+ <v1>: .+ <v1>:
[^:]+: 8b010000 add x0, x0, x1 [^:]+: 8b010000 add x0, x0, x1
[^:]+: 00000000 \.inst 0x00000000 ; undefined [^:]+: 00000000 udf #0
Disassembly of section \.func2: Disassembly of section \.func2:
@ -25,12 +25,12 @@ Disassembly of section \.func3:
[^:]+: 8b010000 add x0, x0, x1 [^:]+: 8b010000 add x0, x0, x1
[^:]+: 8b010000 add x0, x0, x1 [^:]+: 8b010000 add x0, x0, x1
[^:]+: 8b010000 add x0, x0, x1 [^:]+: 8b010000 add x0, x0, x1
[^:]+: 00000000 \.inst 0x00000000 ; undefined [^:]+: 00000000 udf #0
Disassembly of section \.rodata: Disassembly of section \.rodata:
.+ <\.rodata>: .+ <\.rodata>:
[^:]+: 00000000 \.inst 0x00000000 ; undefined [^:]+: 00000000 udf #0
Disassembly of section .global: Disassembly of section .global:

6
binutils/testsuite/binutils-all/aarch64/out-of-order-all.d
View File

@ -20,7 +20,7 @@ Disassembly of section \.func1:
.+ <v1>: .+ <v1>:
[^:]+: 8b010000 add x0, x0, x1 [^:]+: 8b010000 add x0, x0, x1
[^:]+: 00000000 \.inst 0x00000000 ; undefined [^:]+: 00000000 udf #0
Disassembly of section \.func3: Disassembly of section \.func3:
@ -30,9 +30,9 @@ Disassembly of section \.func3:
[^:]+: 8b010000 add x0, x0, x1 [^:]+: 8b010000 add x0, x0, x1
[^:]+: 8b010000 add x0, x0, x1 [^:]+: 8b010000 add x0, x0, x1
[^:]+: 8b010000 add x0, x0, x1 [^:]+: 8b010000 add x0, x0, x1
[^:]+: 00000000 \.inst 0x00000000 ; undefined [^:]+: 00000000 udf #0
Disassembly of section \.rodata: Disassembly of section \.rodata:
.+ <\.rodata>: .+ <\.rodata>:
[^:]+: 00000000 \.inst 0x00000000 ; undefined [^:]+: 00000000 udf #0

11
gas/ChangeLog
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@ -1,3 +1,14 @@
2020-04-30 Alex Coplan <alex.coplan@arm.com>
* config/tc-aarch64.c (fix_insn): Implement for
AARCH64_OPND_UNDEFINED.
(parse_operands): Implement for AARCH64_OPND_UNDEFINED.
* testsuite/gas/aarch64/udf.s: New.
* testsuite/gas/aarch64/udf.d: New.
* testsuite/gas/aarch64/udf-invalid.s: New.
* testsuite/gas/aarch64/udf-invalid.l: New.
* testsuite/gas/aarch64/udf-invalid.d: New.
2020-04-30 Yoshinori Sato <ysato@users.sourceforge.jp> 2020-04-30 Yoshinori Sato <ysato@users.sourceforge.jp>
* config/tc-rx.c (elf_flags): Reset default value. * config/tc-rx.c (elf_flags): Reset default value.

4
gas/config/tc-aarch64.c
View File

@ -6149,6 +6149,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
break; break;
case AARCH64_OPND_EXCEPTION: case AARCH64_OPND_EXCEPTION:
case AARCH64_OPND_UNDEFINED:
po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp, po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp,
imm_reg_type)); imm_reg_type));
assign_imm_if_const_or_fixup_later (&inst.reloc, info, assign_imm_if_const_or_fixup_later (&inst.reloc, info,
@ -7745,11 +7746,12 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value)
switch (opnd) switch (opnd)
{ {
case AARCH64_OPND_EXCEPTION: case AARCH64_OPND_EXCEPTION:
case AARCH64_OPND_UNDEFINED:
if (unsigned_overflow (value, 16)) if (unsigned_overflow (value, 16))
as_bad_where (fixP->fx_file, fixP->fx_line, as_bad_where (fixP->fx_file, fixP->fx_line,
_("immediate out of range")); _("immediate out of range"));
insn = get_aarch64_insn (buf); insn = get_aarch64_insn (buf);
insn |= encode_svc_imm (value); insn |= (opnd == AARCH64_OPND_EXCEPTION) ? encode_svc_imm (value) : value;
put_aarch64_insn (buf, insn); put_aarch64_insn (buf, insn);
break; break;

3
gas/testsuite/gas/aarch64/udf-invalid.d Normal file
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@ -0,0 +1,3 @@
#name: invalid udf instructions
#source: udf-invalid.s
#error_output: udf-invalid.l

4
gas/testsuite/gas/aarch64/udf-invalid.l Normal file
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@ -0,0 +1,4 @@
[^:]*: Assembler messages:
.*: Error: immediate value out of range 0 to 65535 at operand 1 -- `udf #65536'
.*: Error: immediate value out of range 0 to 65535 at operand 1 -- `udf 0xeffff'
.*: Error: immediate value out of range 0 to 65535 at operand 1 -- `udf -1'

6
gas/testsuite/gas/aarch64/udf-invalid.s Normal file
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@ -0,0 +1,6 @@
// Instructions in this file are invalid.
// See udf.s for valid instructions.
.text
udf #65536
udf 0xeffff
udf -1

9
gas/testsuite/gas/aarch64/udf.d Normal file
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@ -0,0 +1,9 @@
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0+ <.*>:
.*: 0000002a udf #42
.*: 0000ffff udf #65535

5
gas/testsuite/gas/aarch64/udf.s Normal file
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@ -0,0 +1,5 @@
// Test file for AArch64 udf.
.text
udf #42
udf #65535

5
include/ChangeLog
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@ -1,3 +1,8 @@
2020-04-30 Alex Coplan <alex.coplan@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add
AARCH64_OPND_UNDEFINED.
2020-04-23 Anton Kolesov <anton.kolesov@synopsys.com> 2020-04-23 Anton Kolesov <anton.kolesov@synopsys.com>
* elf/common.h (NT_ARC_V2): New macro definitions. * elf/common.h (NT_ARC_V2): New macro definitions.

1
include/opcode/aarch64.h
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@ -272,6 +272,7 @@ enum aarch64_opnd
AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */ AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */
AARCH64_OPND_BIT_NUM, /* Immediate. */ AARCH64_OPND_BIT_NUM, /* Immediate. */
AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */
AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */ AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for

7
ld/ChangeLog
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@ -1,3 +1,10 @@
2020-04-30 Alex Coplan <alex.coplan@arm.com>
* testsuite/ld-aarch64/erratum843419_tls_ie.d: Use udf in disassembly.
* testsuite/ld-aarch64/farcall-b-section.d: Likewise.
* testsuite/ld-aarch64/farcall-back.d: Likewise.
* testsuite/ld-aarch64/farcall-bl-section.d: Likewise.
2020-04-30 Nick Clifton <nickc@redhat.com> 2020-04-30 Nick Clifton <nickc@redhat.com>
* testsuite/ld-elf/compress1c.d: XFAIL if thet target linker does * testsuite/ld-elf/compress1c.d: XFAIL if thet target linker does

4
ld/testsuite/ld-aarch64/erratum843419_tls_ie.d
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@ -23,10 +23,10 @@ Disassembly of section .e843419:
[ ]*20001010: 0b0700e0 add w0, w7, w7 [ ]*20001010: 0b0700e0 add w0, w7, w7
[ ]*20001014: 910043ff add sp, sp, #0x10 [ ]*20001014: 910043ff add sp, sp, #0x10
[ ]*20001018: d65f03c0 ret [ ]*20001018: d65f03c0 ret
[ ]*2000101c: 00000000 .inst 0x00000000 ; undefined [ ]*2000101c: 00000000 udf #0
[ ]*20001020: 14000400 b 20002020 <e843419\+0x1028> [ ]*20001020: 14000400 b 20002020 <e843419\+0x1028>
[ ]*20001024: d503201f nop [ ]*20001024: d503201f nop
[ ]*20001028: 00000000 .inst 0x00000000 ; undefined [ ]*20001028: 00000000 udf #0
[ ]*2000102c: 17fffff7 b 20001008 <e843419\+0x10> [ ]*2000102c: 17fffff7 b 20001008 <e843419\+0x10>
... ...

2
ld/testsuite/ld-aarch64/farcall-b-section.d
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@ -19,7 +19,7 @@ Disassembly of section .text:
1018: 90040010 adrp x16, 8001000 <bar> 1018: 90040010 adrp x16, 8001000 <bar>
101c: 91001210 add x16, x16, #0x4 101c: 91001210 add x16, x16, #0x4
1020: d61f0200 br x16 1020: d61f0200 br x16
1024: 00000000 .inst 0x00000000 ; undefined 1024: 00000000 udf #0
.* <___veneer>: .* <___veneer>:
1028: 90040010 adrp x16, 8001000 <bar> 1028: 90040010 adrp x16, 8001000 <bar>

2
ld/testsuite/ld-aarch64/farcall-back.d
View File

@ -27,7 +27,7 @@ Disassembly of section .text:
2028: f07ffff0 adrp x16, 100001000 <bar1\+0x1000> 2028: f07ffff0 adrp x16, 100001000 <bar1\+0x1000>
202c: 91002210 add x16, x16, #0x8 202c: 91002210 add x16, x16, #0x8
2030: d61f0200 br x16 2030: d61f0200 br x16
2034: 00000000 .inst 0x00000000 ; undefined 2034: 00000000 udf #0
0000000000002038 <__bar3_veneer>: 0000000000002038 <__bar3_veneer>:
2038: 58000090 ldr x16, 2048 <__bar3_veneer\+0x10> 2038: 58000090 ldr x16, 2048 <__bar3_veneer\+0x10>

2
ld/testsuite/ld-aarch64/farcall-bl-section.d
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@ -19,7 +19,7 @@ Disassembly of section .text:
1018: 90040010 adrp x16, 8001000 <bar> 1018: 90040010 adrp x16, 8001000 <bar>
101c: 91001210 add x16, x16, #0x4 101c: 91001210 add x16, x16, #0x4
1020: d61f0200 br x16 1020: d61f0200 br x16
1024: 00000000 .inst 0x00000000 ; undefined 1024: 00000000 udf #0
.* <___veneer>: .* <___veneer>:
1028: 90040010 adrp x16, 8001000 <bar> 1028: 90040010 adrp x16, 8001000 <bar>

12
opcodes/ChangeLog
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@ -1,3 +1,15 @@
2020-04-30 Alex Coplan <alex.coplan@arm.com>
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
* aarch64-opc.c (fields): Add entry for FLD_imm16_2.
(operand_general_constraint_met_p): validate
AARCH64_OPND_UNDEFINED.
* aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
for FLD_imm16_2.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
2020-04-29 Nick Clifton <nickc@redhat.com> 2020-04-29 Nick Clifton <nickc@redhat.com>
PR 22699 PR 22699

785
opcodes/aarch64-asm-2.c
View File

@ -197,396 +197,396 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 746: /* umsubl */ case 746: /* umsubl */
value = 746; /* --> umsubl. */ value = 746; /* --> umsubl. */
break; break;
case 758: /* ror */ case 759: /* ror */
case 757: /* extr */ case 758: /* extr */
value = 757; /* --> extr. */ value = 758; /* --> extr. */
break; break;
case 991: /* bic */ case 992: /* bic */
case 990: /* and */ case 991: /* and */
value = 990; /* --> and. */ value = 991; /* --> and. */
break; break;
case 993: /* mov */ case 994: /* mov */
case 992: /* orr */ case 993: /* orr */
value = 992; /* --> orr. */ value = 993; /* --> orr. */
break; break;
case 996: /* tst */ case 997: /* tst */
case 995: /* ands */ case 996: /* ands */
value = 995; /* --> ands. */ value = 996; /* --> ands. */
break; break;
case 1001: /* uxtw */ case 1002: /* uxtw */
case 1000: /* mov */ case 1001: /* mov */
case 999: /* orr */ case 1000: /* orr */
value = 999; /* --> orr. */ value = 1000; /* --> orr. */
break; break;
case 1003: /* mvn */ case 1004: /* mvn */
case 1002: /* orn */ case 1003: /* orn */
value = 1002; /* --> orn. */ value = 1003; /* --> orn. */
break; break;
case 1007: /* tst */ case 1008: /* tst */
case 1006: /* ands */ case 1007: /* ands */
value = 1006; /* --> ands. */ value = 1007; /* --> ands. */
break; break;
case 1133: /* staddb */ case 1134: /* staddb */
case 1037: /* ldaddb */ case 1038: /* ldaddb */
value = 1037; /* --> ldaddb. */ value = 1038; /* --> ldaddb. */
break; break;
case 1134: /* staddh */ case 1135: /* staddh */
case 1038: /* ldaddh */ case 1039: /* ldaddh */
value = 1038; /* --> ldaddh. */ value = 1039; /* --> ldaddh. */
break; break;
case 1135: /* stadd */ case 1136: /* stadd */
case 1039: /* ldadd */ case 1040: /* ldadd */
value = 1039; /* --> ldadd. */ value = 1040; /* --> ldadd. */
break; break;
case 1136: /* staddlb */ case 1137: /* staddlb */
case 1041: /* ldaddlb */ case 1042: /* ldaddlb */
value = 1041; /* --> ldaddlb. */ value = 1042; /* --> ldaddlb. */
break; break;
case 1137: /* staddlh */ case 1138: /* staddlh */
case 1044: /* ldaddlh */ case 1045: /* ldaddlh */
value = 1044; /* --> ldaddlh. */ value = 1045; /* --> ldaddlh. */
break; break;
case 1138: /* staddl */ case 1139: /* staddl */
case 1047: /* ldaddl */ case 1048: /* ldaddl */
value = 1047; /* --> ldaddl. */ value = 1048; /* --> ldaddl. */
break; break;
case 1139: /* stclrb */ case 1140: /* stclrb */
case 1049: /* ldclrb */ case 1050: /* ldclrb */
value = 1049; /* --> ldclrb. */ value = 1050; /* --> ldclrb. */
break; break;
case 1140: /* stclrh */ case 1141: /* stclrh */
case 1050: /* ldclrh */ case 1051: /* ldclrh */
value = 1050; /* --> ldclrh. */ value = 1051; /* --> ldclrh. */
break; break;
case 1141: /* stclr */ case 1142: /* stclr */
case 1051: /* ldclr */ case 1052: /* ldclr */
value = 1051; /* --> ldclr. */ value = 1052; /* --> ldclr. */
break; break;
case 1142: /* stclrlb */ case 1143: /* stclrlb */
case 1053: /* ldclrlb */ case 1054: /* ldclrlb */
value = 1053; /* --> ldclrlb. */ value = 1054; /* --> ldclrlb. */
break; break;
case 1143: /* stclrlh */ case 1144: /* stclrlh */
case 1056: /* ldclrlh */ case 1057: /* ldclrlh */
value = 1056; /* --> ldclrlh. */ value = 1057; /* --> ldclrlh. */
break; break;
case 1144: /* stclrl */ case 1145: /* stclrl */
case 1059: /* ldclrl */ case 1060: /* ldclrl */
value = 1059; /* --> ldclrl. */ value = 1060; /* --> ldclrl. */
break; break;
case 1145: /* steorb */ case 1146: /* steorb */
case 1061: /* ldeorb */ case 1062: /* ldeorb */
value = 1061; /* --> ldeorb. */ value = 1062; /* --> ldeorb. */
break; break;
case 1146: /* steorh */ case 1147: /* steorh */
case 1062: /* ldeorh */ case 1063: /* ldeorh */
value = 1062; /* --> ldeorh. */ value = 1063; /* --> ldeorh. */
break; break;
case 1147: /* steor */ case 1148: /* steor */
case 1063: /* ldeor */ case 1064: /* ldeor */
value = 1063; /* --> ldeor. */ value = 1064; /* --> ldeor. */
break; break;
case 1148: /* steorlb */ case 1149: /* steorlb */
case 1065: /* ldeorlb */ case 1066: /* ldeorlb */
value = 1065; /* --> ldeorlb. */ value = 1066; /* --> ldeorlb. */
break; break;
case 1149: /* steorlh */ case 1150: /* steorlh */
case 1068: /* ldeorlh */ case 1069: /* ldeorlh */
value = 1068; /* --> ldeorlh. */ value = 1069; /* --> ldeorlh. */
break; break;
case 1150: /* steorl */ case 1151: /* steorl */
case 1071: /* ldeorl */ case 1072: /* ldeorl */
value = 1071; /* --> ldeorl. */ value = 1072; /* --> ldeorl. */
break; break;
case 1151: /* stsetb */ case 1152: /* stsetb */
case 1073: /* ldsetb */ case 1074: /* ldsetb */
value = 1073; /* --> ldsetb. */ value = 1074; /* --> ldsetb. */
break; break;
case 1152: /* stseth */ case 1153: /* stseth */
case 1074: /* ldseth */ case 1075: /* ldseth */
value = 1074; /* --> ldseth. */ value = 1075; /* --> ldseth. */
break; break;
case 1153: /* stset */ case 1154: /* stset */
case 1075: /* ldset */ case 1076: /* ldset */
value = 1075; /* --> ldset. */ value = 1076; /* --> ldset. */
break; break;
case 1154: /* stsetlb */ case 1155: /* stsetlb */
case 1077: /* ldsetlb */ case 1078: /* ldsetlb */
value = 1077; /* --> ldsetlb. */ value = 1078; /* --> ldsetlb. */
break; break;
case 1155: /* stsetlh */ case 1156: /* stsetlh */
case 1080: /* ldsetlh */ case 1081: /* ldsetlh */
value = 1080; /* --> ldsetlh. */ value = 1081; /* --> ldsetlh. */
break; break;
case 1156: /* stsetl */ case 1157: /* stsetl */
case 1083: /* ldsetl */ case 1084: /* ldsetl */
value = 1083; /* --> ldsetl. */ value = 1084; /* --> ldsetl. */
break; break;
case 1157: /* stsmaxb */ case 1158: /* stsmaxb */
case 1085: /* ldsmaxb */ case 1086: /* ldsmaxb */
value = 1085; /* --> ldsmaxb. */ value = 1086; /* --> ldsmaxb. */
break; break;
case 1158: /* stsmaxh */ case 1159: /* stsmaxh */
case 1086: /* ldsmaxh */ case 1087: /* ldsmaxh */
value = 1086; /* --> ldsmaxh. */ value = 1087; /* --> ldsmaxh. */
break; break;
case 1159: /* stsmax */ case 1160: /* stsmax */
case 1087: /* ldsmax */ case 1088: /* ldsmax */
value = 1087; /* --> ldsmax. */ value = 1088; /* --> ldsmax. */
break; break;
case 1160: /* stsmaxlb */ case 1161: /* stsmaxlb */
case 1089: /* ldsmaxlb */ case 1090: /* ldsmaxlb */
value = 1089; /* --> ldsmaxlb. */ value = 1090; /* --> ldsmaxlb. */
break; break;
case 1161: /* stsmaxlh */ case 1162: /* stsmaxlh */
case 1092: /* ldsmaxlh */ case 1093: /* ldsmaxlh */
value = 1092; /* --> ldsmaxlh. */ value = 1093; /* --> ldsmaxlh. */
break; break;
case 1162: /* stsmaxl */ case 1163: /* stsmaxl */
case 1095: /* ldsmaxl */ case 1096: /* ldsmaxl */
value = 1095; /* --> ldsmaxl. */ value = 1096; /* --> ldsmaxl. */
break; break;
case 1163: /* stsminb */ case 1164: /* stsminb */
case 1097: /* ldsminb */ case 1098: /* ldsminb */
value = 1097; /* --> ldsminb. */ value = 1098; /* --> ldsminb. */
break; break;
case 1164: /* stsminh */ case 1165: /* stsminh */
case 1098: /* ldsminh */ case 1099: /* ldsminh */
value = 1098; /* --> ldsminh. */ value = 1099; /* --> ldsminh. */
break; break;
case 1165: /* stsmin */ case 1166: /* stsmin */
case 1099: /* ldsmin */ case 1100: /* ldsmin */
value = 1099; /* --> ldsmin. */ value = 1100; /* --> ldsmin. */
break; break;
case 1166: /* stsminlb */ case 1167: /* stsminlb */
case 1101: /* ldsminlb */ case 1102: /* ldsminlb */
value = 1101; /* --> ldsminlb. */ value = 1102; /* --> ldsminlb. */
break; break;
case 1167: /* stsminlh */ case 1168: /* stsminlh */
case 1104: /* ldsminlh */ case 1105: /* ldsminlh */
value = 1104; /* --> ldsminlh. */ value = 1105; /* --> ldsminlh. */
break; break;
case 1168: /* stsminl */ case 1169: /* stsminl */
case 1107: /* ldsminl */ case 1108: /* ldsminl */
value = 1107; /* --> ldsminl. */ value = 1108; /* --> ldsminl. */
break; break;
case 1169: /* stumaxb */ case 1170: /* stumaxb */
case 1109: /* ldumaxb */ case 1110: /* ldumaxb */
value = 1109; /* --> ldumaxb. */ value = 1110; /* --> ldumaxb. */
break; break;
case 1170: /* stumaxh */ case 1171: /* stumaxh */
case 1110: /* ldumaxh */ case 1111: /* ldumaxh */
value = 1110; /* --> ldumaxh. */ value = 1111; /* --> ldumaxh. */
break; break;
case 1171: /* stumax */ case 1172: /* stumax */
case 1111: /* ldumax */ case 1112: /* ldumax */
value = 1111; /* --> ldumax. */ value = 1112; /* --> ldumax. */
break; break;
case 1172: /* stumaxlb */ case 1173: /* stumaxlb */
case 1113: /* ldumaxlb */ case 1114: /* ldumaxlb */
value = 1113; /* --> ldumaxlb. */ value = 1114; /* --> ldumaxlb. */
break; break;
case 1173: /* stumaxlh */ case 1174: /* stumaxlh */
case 1116: /* ldumaxlh */ case 1117: /* ldumaxlh */
value = 1116; /* --> ldumaxlh. */ value = 1117; /* --> ldumaxlh. */
break; break;
case 1174: /* stumaxl */ case 1175: /* stumaxl */
case 1119: /* ldumaxl */ case 1120: /* ldumaxl */
value = 1119; /* --> ldumaxl. */ value = 1120; /* --> ldumaxl. */
break; break;
case 1175: /* stuminb */ case 1176: /* stuminb */
case 1121: /* lduminb */ case 1122: /* lduminb */
value = 1121; /* --> lduminb. */ value = 1122; /* --> lduminb. */
break; break;
case 1176: /* stuminh */ case 1177: /* stuminh */
case 1122: /* lduminh */ case 1123: /* lduminh */
value = 1122; /* --> lduminh. */ value = 1123; /* --> lduminh. */
break; break;
case 1177: /* stumin */ case 1178: /* stumin */
case 1123: /* ldumin */ case 1124: /* ldumin */
value = 1123; /* --> ldumin. */ value = 1124; /* --> ldumin. */
break; break;
case 1178: /* stuminlb */ case 1179: /* stuminlb */
case 1125: /* lduminlb */ case 1126: /* lduminlb */
value = 1125; /* --> lduminlb. */ value = 1126; /* --> lduminlb. */
break; break;
case 1179: /* stuminlh */ case 1180: /* stuminlh */
case 1128: /* lduminlh */ case 1129: /* lduminlh */
value = 1128; /* --> lduminlh. */ value = 1129; /* --> lduminlh. */
break; break;
case 1180: /* stuminl */ case 1181: /* stuminl */
case 1131: /* lduminl */ case 1132: /* lduminl */
value = 1131; /* --> lduminl. */ value = 1132; /* --> lduminl. */
break; break;
case 1182: /* mov */ case 1183: /* mov */
case 1181: /* movn */ case 1182: /* movn */
value = 1181; /* --> movn. */ value = 1182; /* --> movn. */
break; break;
case 1184: /* mov */ case 1185: /* mov */
case 1183: /* movz */ case 1184: /* movz */
value = 1183; /* --> movz. */ value = 1184; /* --> movz. */
break; break;
case 1237: /* autibsp */ case 1238: /* autibsp */
case 1236: /* autibz */ case 1237: /* autibz */
case 1235: /* autiasp */ case 1236: /* autiasp */
case 1234: /* autiaz */ case 1235: /* autiaz */
case 1233: /* pacibsp */ case 1234: /* pacibsp */
case 1232: /* pacibz */ case 1233: /* pacibz */
case 1231: /* paciasp */ case 1232: /* paciasp */
case 1230: /* paciaz */ case 1231: /* paciaz */
case 1210: /* tsb */ case 1211: /* tsb */
case 1209: /* psb */ case 1210: /* psb */
case 1208: /* esb */ case 1209: /* esb */
case 1207: /* autib1716 */ case 1208: /* autib1716 */
case 1206: /* autia1716 */ case 1207: /* autia1716 */
case 1205: /* pacib1716 */ case 1206: /* pacib1716 */
case 1204: /* pacia1716 */ case 1205: /* pacia1716 */
case 1203: /* xpaclri */ case 1204: /* xpaclri */
case 1201: /* sevl */ case 1202: /* sevl */
case 1200: /* sev */ case 1201: /* sev */
case 1199: /* wfi */ case 1200: /* wfi */
case 1198: /* wfe */ case 1199: /* wfe */
case 1197: /* yield */ case 1198: /* yield */
case 1196: /* bti */ case 1197: /* bti */
case 1195: /* csdb */ case 1196: /* csdb */
case 1194: /* nop */ case 1195: /* nop */
case 1193: /* hint */ case 1194: /* hint */
value = 1193; /* --> hint. */ value = 1194; /* --> hint. */
break; break;
case 1214: /* pssbb */ case 1215: /* pssbb */
case 1213: /* ssbb */ case 1214: /* ssbb */
case 1212: /* dsb */ case 1213: /* dsb */
value = 1212; /* --> dsb. */ value = 1213; /* --> dsb. */
break; break;
case 1225: /* cpp */ case 1226: /* cpp */
case 1224: /* dvp */ case 1225: /* dvp */
case 1223: /* cfp */ case 1224: /* cfp */
case 1222: /* tlbi */ case 1223: /* tlbi */
case 1221: /* ic */ case 1222: /* ic */
case 1220: /* dc */ case 1221: /* dc */
case 1219: /* at */ case 1220: /* at */
case 1218: /* sys */ case 1219: /* sys */
value = 1218; /* --> sys. */ value = 1219; /* --> sys. */
break; break;
case 2035: /* bic */ case 2036: /* bic */
case 1285: /* and */ case 1286: /* and */
value = 1285; /* --> and. */ value = 1286; /* --> and. */
break; break;
case 1268: /* mov */ case 1269: /* mov */
case 1287: /* and */ case 1288: /* and */
value = 1287; /* --> and. */ value = 1288; /* --> and. */
break; break;
case 1272: /* movs */ case 1273: /* movs */
case 1288: /* ands */ case 1289: /* ands */
value = 1288; /* --> ands. */ value = 1289; /* --> ands. */
break; break;
case 2036: /* cmple */ case 2037: /* cmple */
case 1323: /* cmpge */ case 1324: /* cmpge */
value = 1323; /* --> cmpge. */ value = 1324; /* --> cmpge. */
break; break;
case 2039: /* cmplt */ case 2040: /* cmplt */
case 1326: /* cmpgt */ case 1327: /* cmpgt */
value = 1326; /* --> cmpgt. */ value = 1327; /* --> cmpgt. */
break; break;
case 2037: /* cmplo */ case 2038: /* cmplo */
case 1328: /* cmphi */ case 1329: /* cmphi */
value = 1328; /* --> cmphi. */ value = 1329; /* --> cmphi. */
break; break;
case 2038: /* cmpls */ case 2039: /* cmpls */
case 1331: /* cmphs */ case 1332: /* cmphs */
value = 1331; /* --> cmphs. */ value = 1332; /* --> cmphs. */
break; break;
case 1265: /* mov */ case 1266: /* mov */
case 1353: /* cpy */
value = 1353; /* --> cpy. */
break;
case 1267: /* mov */
case 1354: /* cpy */ case 1354: /* cpy */
value = 1354; /* --> cpy. */ value = 1354; /* --> cpy. */
break; break;
case 2046: /* fmov */ case 1268: /* mov */
case 1270: /* mov */
case 1355: /* cpy */ case 1355: /* cpy */
value = 1355; /* --> cpy. */ value = 1355; /* --> cpy. */
break; break;
case 1260: /* mov */ case 2047: /* fmov */
case 1367: /* dup */ case 1271: /* mov */
value = 1367; /* --> dup. */ case 1356: /* cpy */
value = 1356; /* --> cpy. */
break; break;
case 1262: /* mov */ case 1261: /* mov */
case 1259: /* mov */
case 1368: /* dup */ case 1368: /* dup */
value = 1368; /* --> dup. */ value = 1368; /* --> dup. */
break; break;
case 2045: /* fmov */ case 1263: /* mov */
case 1264: /* mov */ case 1260: /* mov */
case 1369: /* dup */ case 1369: /* dup */
value = 1369; /* --> dup. */ value = 1369; /* --> dup. */
break; break;
case 1263: /* mov */ case 2046: /* fmov */
case 1370: /* dupm */ case 1265: /* mov */
value = 1370; /* --> dupm. */ case 1370: /* dup */
value = 1370; /* --> dup. */
break; break;
case 2040: /* eon */ case 1264: /* mov */
case 1372: /* eor */ case 1371: /* dupm */
value = 1372; /* --> eor. */ value = 1371; /* --> dupm. */
break; break;
case 1273: /* not */ case 2041: /* eon */
case 1374: /* eor */ case 1373: /* eor */
value = 1374; /* --> eor. */ value = 1373; /* --> eor. */
break; break;
case 1274: /* nots */ case 1274: /* not */
case 1375: /* eors */ case 1375: /* eor */
value = 1375; /* --> eors. */ value = 1375; /* --> eor. */
break; break;
case 2041: /* facle */ case 1275: /* nots */
case 1380: /* facge */ case 1376: /* eors */
value = 1380; /* --> facge. */ value = 1376; /* --> eors. */
break; break;
case 2042: /* faclt */ case 2042: /* facle */
case 1381: /* facgt */ case 1381: /* facge */
value = 1381; /* --> facgt. */ value = 1381; /* --> facge. */
break; break;
case 2043: /* fcmle */ case 2043: /* faclt */
case 1394: /* fcmge */ case 1382: /* facgt */
value = 1394; /* --> fcmge. */ value = 1382; /* --> facgt. */
break; break;
case 2044: /* fcmlt */ case 2044: /* fcmle */
case 1396: /* fcmgt */ case 1395: /* fcmge */
value = 1396; /* --> fcmgt. */ value = 1395; /* --> fcmge. */
break;
case 2045: /* fcmlt */
case 1397: /* fcmgt */
value = 1397; /* --> fcmgt. */
break;
case 1258: /* fmov */
case 1403: /* fcpy */
value = 1403; /* --> fcpy. */
break; break;
case 1257: /* fmov */ case 1257: /* fmov */
case 1402: /* fcpy */ case 1426: /* fdup */
value = 1402; /* --> fcpy. */ value = 1426; /* --> fdup. */
break; break;
case 1256: /* fmov */ case 1259: /* mov */
case 1425: /* fdup */
value = 1425; /* --> fdup. */
break;
case 1258: /* mov */
case 1756: /* orr */
value = 1756; /* --> orr. */
break;
case 2047: /* orn */
case 1757: /* orr */ case 1757: /* orr */
value = 1757; /* --> orr. */ value = 1757; /* --> orr. */
break; break;
case 1261: /* mov */ case 2048: /* orn */
case 1759: /* orr */ case 1758: /* orr */
value = 1759; /* --> orr. */ value = 1758; /* --> orr. */
break; break;
case 1271: /* movs */ case 1262: /* mov */
case 1760: /* orrs */ case 1760: /* orr */
value = 1760; /* --> orrs. */ value = 1760; /* --> orr. */
break; break;
case 1266: /* mov */ case 1272: /* movs */
case 1822: /* sel */ case 1761: /* orrs */
value = 1822; /* --> sel. */ value = 1761; /* --> orrs. */
break; break;
case 1269: /* mov */ case 1267: /* mov */
case 1823: /* sel */ case 1823: /* sel */
value = 1823; /* --> sel. */ value = 1823; /* --> sel. */
break; break;
case 1270: /* mov */
case 1824: /* sel */
value = 1824; /* --> sel. */
break;
default: return NULL; default: return NULL;
} }
@ -629,7 +629,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 28: case 28:
case 29: case 29:
case 30: case 30:
case 163:
case 164: case 164:
case 165: case 165:
case 166: case 166:
@ -639,7 +638,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 170: case 170:
case 171: case 171:
case 172: case 172:
case 187: case 173:
case 188: case 188:
case 189: case 189:
case 190: case 190:
@ -648,8 +647,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 193: case 193:
case 194: case 194:
case 195: case 195:
case 201: case 196:
case 204: case 202:
case 205:
return aarch64_ins_regno (self, info, code, inst, errors); return aarch64_ins_regno (self, info, code, inst, errors);
case 14: case 14:
return aarch64_ins_reg_extended (self, info, code, inst, errors); return aarch64_ins_reg_extended (self, info, code, inst, errors);
@ -661,7 +661,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 32: case 32:
case 33: case 33:
case 34: case 34:
case 207: case 208:
return aarch64_ins_reglane (self, info, code, inst, errors); return aarch64_ins_reglane (self, info, code, inst, errors);
case 35: case 35:
return aarch64_ins_reglist (self, info, code, inst, errors); return aarch64_ins_reglist (self, info, code, inst, errors);
@ -691,13 +691,13 @@ aarch64_insert_operand (const aarch64_operand *self,
case 65: case 65:
case 66: case 66:
case 67: case 67:
case 79: case 68:
case 80: case 80:
case 81: case 81:
case 82: case 82:
case 160: case 83:
case 162: case 161:
case 179: case 163:
case 180: case 180:
case 181: case 181:
case 182: case 182:
@ -705,7 +705,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 184: case 184:
case 185: case 185:
case 186: case 186:
case 206: case 187:
case 207:
return aarch64_ins_imm (self, info, code, inst, errors); return aarch64_ins_imm (self, info, code, inst, errors);
case 43: case 43:
case 44: case 44:
@ -715,84 +716,83 @@ aarch64_insert_operand (const aarch64_operand *self,
case 47: case 47:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors); return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
case 51: case 51:
case 150: case 151:
return aarch64_ins_fpimm (self, info, code, inst, errors); return aarch64_ins_fpimm (self, info, code, inst, errors);
case 68:
case 158:
return aarch64_ins_limm (self, info, code, inst, errors);
case 69: case 69:
return aarch64_ins_aimm (self, info, code, inst, errors); case 159:
return aarch64_ins_limm (self, info, code, inst, errors);
case 70: case 70:
return aarch64_ins_imm_half (self, info, code, inst, errors); return aarch64_ins_aimm (self, info, code, inst, errors);
case 71: case 71:
return aarch64_ins_imm_half (self, info, code, inst, errors);
case 72:
return aarch64_ins_fbits (self, info, code, inst, errors); return aarch64_ins_fbits (self, info, code, inst, errors);
case 73:
case 74: case 74:
case 155:
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 75: case 75:
case 154:
case 156: case 156:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 76: case 76:
case 155:
case 157:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 77: case 77:
case 78:
return aarch64_ins_cond (self, info, code, inst, errors); return aarch64_ins_cond (self, info, code, inst, errors);
case 83:
case 92:
return aarch64_ins_addr_simple (self, info, code, inst, errors);
case 84: case 84:
return aarch64_ins_addr_regoff (self, info, code, inst, errors); case 93:
return aarch64_ins_addr_simple (self, info, code, inst, errors);
case 85: case 85:
return aarch64_ins_addr_regoff (self, info, code, inst, errors);
case 86: case 86:
case 87: case 87:
case 89:
case 91:
return aarch64_ins_addr_simm (self, info, code, inst, errors);
case 88: case 88:
return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
case 90: case 90:
case 92:
return aarch64_ins_addr_simm (self, info, code, inst, errors);
case 89:
return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
case 91:
return aarch64_ins_addr_uimm12 (self, info, code, inst, errors); return aarch64_ins_addr_uimm12 (self, info, code, inst, errors);
case 93:
return aarch64_ins_addr_offset (self, info, code, inst, errors);
case 94: case 94:
return aarch64_ins_simd_addr_post (self, info, code, inst, errors); return aarch64_ins_addr_offset (self, info, code, inst, errors);
case 95: case 95:
return aarch64_ins_sysreg (self, info, code, inst, errors); return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
case 96: case 96:
return aarch64_ins_pstatefield (self, info, code, inst, errors); return aarch64_ins_sysreg (self, info, code, inst, errors);
case 97: case 97:
return aarch64_ins_pstatefield (self, info, code, inst, errors);
case 98: case 98:
case 99: case 99:
case 100: case 100:
case 101: case 101:
return aarch64_ins_sysins_op (self, info, code, inst, errors);
case 102: case 102:
return aarch64_ins_sysins_op (self, info, code, inst, errors);
case 103: case 103:
return aarch64_ins_barrier (self, info, code, inst, errors);
case 104: case 104:
return aarch64_ins_prfop (self, info, code, inst, errors); return aarch64_ins_barrier (self, info, code, inst, errors);
case 105: case 105:
return aarch64_ins_none (self, info, code, inst, errors); return aarch64_ins_prfop (self, info, code, inst, errors);
case 106: case 106:
return aarch64_ins_hint (self, info, code, inst, errors); return aarch64_ins_none (self, info, code, inst, errors);
case 107: case 107:
return aarch64_ins_hint (self, info, code, inst, errors);
case 108: case 108:
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 109: case 109:
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 110: case 110:
case 111: case 111:
case 112: case 112:
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 113: case 113:
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 114: case 114:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 115: case 115:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 116: case 116:
case 117: case 117:
case 118: case 118:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 119: case 119:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 120: case 120:
case 121: case 121:
case 122: case 122:
@ -806,8 +806,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 130: case 130:
case 131: case 131:
case 132: case 132:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 133: case 133:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 134: case 134:
case 135: case 135:
case 136: case 136:
@ -815,52 +815,53 @@ aarch64_insert_operand (const aarch64_operand *self,
case 138: case 138:
case 139: case 139:
case 140: case 140:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 141: case 141:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 142: case 142:
case 143: case 143:
case 144: case 144:
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 145: case 145:
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 146: case 146:
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 147: case 147:
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 148: case 148:
return aarch64_ins_sve_aimm (self, info, code, inst, errors); return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 149: case 149:
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
case 150:
return aarch64_ins_sve_asimm (self, info, code, inst, errors); return aarch64_ins_sve_asimm (self, info, code, inst, errors);
case 151:
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 152: case 152:
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 153: case 153:
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
case 154:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors); return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
case 157: case 158:
return aarch64_ins_inv_limm (self, info, code, inst, errors); return aarch64_ins_inv_limm (self, info, code, inst, errors);
case 159: case 160:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors); return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
case 161: case 162:
return aarch64_ins_sve_scale (self, info, code, inst, errors); return aarch64_ins_sve_scale (self, info, code, inst, errors);
case 173:
case 174: case 174:
case 175: case 175:
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 176: case 176:
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 177: case 177:
case 178: case 178:
case 179:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors); return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 196:
case 197: case 197:
case 198: case 198:
case 199: case 199:
case 200: case 200:
case 201:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors); return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
case 202:
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 203: case 203:
case 205: return aarch64_ins_sve_index (self, info, code, inst, errors);
case 204:
case 206:
return aarch64_ins_sve_reglist (self, info, code, inst, errors); return aarch64_ins_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort (); default: assert (0); abort ();
} }

3812
opcodes/aarch64-dis-2.c
View File

File diff suppressed because it is too large Load Diff

53
opcodes/aarch64-opc-2.c
View File

@ -89,6 +89,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM10", OPD_F_SHIFT_BY_4 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "a 10-bit unsigned multiple of 16"}, {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM10", OPD_F_SHIFT_BY_4 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "a 10-bit unsigned multiple of 16"},
{AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_b5, FLD_b40}, "the bit number to be tested"}, {AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_b5, FLD_b40}, "the bit number to be tested"},
{AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "UNDEFINED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_2}, "a 16-bit unsigned immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit signed immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit signed immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"}, {AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"},
@ -241,48 +242,48 @@ const struct aarch64_operand aarch64_operands[] =
static const unsigned op_enum_table [] = static const unsigned op_enum_table [] =
{ {
0, 0,
888,
889, 889,
890, 890,
893, 891,
894, 894,
895, 895,
896, 896,
897, 897,
891,
892,
898, 898,
892,
893,
899, 899,
921, 900,
922, 922,
923, 923,
926, 924,
927, 927,
928, 928,
929, 929,
930, 930,
924,
925,
931, 931,
925,
926,
932, 932,
986, 933,
987, 987,
988, 988,
989, 989,
990,
12, 12,
636, 636,
637, 637,
1181,
1183,
1185,
993,
1184,
1182, 1182,
1184,
1186,
994,
1185,
1183,
318, 318,
624, 624,
635, 635,
634, 634,
991, 992,
631, 631,
628, 628,
620, 620,
@ -292,34 +293,34 @@ static const unsigned op_enum_table [] =
630, 630,
632, 632,
633, 633,
1001, 1002,
664, 664,
667, 667,
670, 670,
665, 665,
668, 668,
824, 825,
178, 178,
179, 179,
180, 180,
181, 181,
516, 516,
758, 759,
389, 389,
391, 391,
413, 413,
415, 415,
1261,
1266,
1259,
1258,
1262, 1262,
1269, 1267,
1271, 1260,
1259,
1263,
1270,
1272, 1272,
1268,
1274,
1273, 1273,
1269,
1275,
1274,
131, 131,
}; };

3
opcodes/aarch64-opc.c
View File

@ -251,6 +251,7 @@ const aarch64_field fields[] =
{ 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */ { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
{ 5, 14 }, /* imm14: in test bit and branch instructions. */ { 5, 14 }, /* imm14: in test bit and branch instructions. */
{ 5, 16 }, /* imm16: in exception instructions. */ { 5, 16 }, /* imm16: in exception instructions. */
{ 0, 16 }, /* imm16_2: in udf instruction. */
{ 0, 26 }, /* imm26: in unconditional branch instructions. */ { 0, 26 }, /* imm26: in unconditional branch instructions. */
{ 10, 6 }, /* imms: in bitfield and logical immediate instructions. */ { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
{ 16, 6 }, /* immr: in bitfield and logical immediate instructions. */ { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
@ -2145,6 +2146,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_NZCV: case AARCH64_OPND_NZCV:
case AARCH64_OPND_CCMP_IMM: case AARCH64_OPND_CCMP_IMM:
case AARCH64_OPND_EXCEPTION: case AARCH64_OPND_EXCEPTION:
case AARCH64_OPND_UNDEFINED:
case AARCH64_OPND_TME_UIMM16: case AARCH64_OPND_TME_UIMM16:
case AARCH64_OPND_UIMM4: case AARCH64_OPND_UIMM4:
case AARCH64_OPND_UIMM4_ADDG: case AARCH64_OPND_UIMM4_ADDG:
@ -3357,6 +3359,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_IMM0: case AARCH64_OPND_IMM0:
case AARCH64_OPND_IMMR: case AARCH64_OPND_IMMR:
case AARCH64_OPND_IMMS: case AARCH64_OPND_IMMS:
case AARCH64_OPND_UNDEFINED:
case AARCH64_OPND_FBITS: case AARCH64_OPND_FBITS:
case AARCH64_OPND_TME_UIMM16: case AARCH64_OPND_TME_UIMM16:
case AARCH64_OPND_SIMM5: case AARCH64_OPND_SIMM5:

1
opcodes/aarch64-opc.h
View File

@ -78,6 +78,7 @@ enum aarch64_field_kind
FLD_imm12, FLD_imm12,
FLD_imm14, FLD_imm14,
FLD_imm16, FLD_imm16,
FLD_imm16_2,
FLD_imm26, FLD_imm26,
FLD_imms, FLD_imms,
FLD_immr, FLD_immr,

3
opcodes/aarch64-tbl.h
View File

@ -3354,6 +3354,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("smc", 0xd4000003, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), CORE_INSN ("smc", 0xd4000003, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0),
CORE_INSN ("brk", 0xd4200000, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), CORE_INSN ("brk", 0xd4200000, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0),
CORE_INSN ("hlt", 0xd4400000, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), CORE_INSN ("hlt", 0xd4400000, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0),
CORE_INSN ("udf", 0x00000000, 0xffff0000, exception, 0, OP1 (UNDEFINED), {}, 0),
CORE_INSN ("dcps1", 0xd4a00001, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), CORE_INSN ("dcps1", 0xd4a00001, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)),
CORE_INSN ("dcps2", 0xd4a00002, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), CORE_INSN ("dcps2", 0xd4a00002, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)),
CORE_INSN ("dcps3", 0xd4a00003, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), CORE_INSN ("dcps3", 0xd4a00003, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)),
@ -5238,6 +5239,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
"the bit number to be tested") \ "the bit number to be tested") \
Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16), \ Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16), \
"a 16-bit unsigned immediate") \ "a 16-bit unsigned immediate") \
Y(IMMEDIATE, imm, "UNDEFINED", 0, F(FLD_imm16_2), \
"a 16-bit unsigned immediate") \
Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5), \ Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5), \
"a 5-bit unsigned immediate") \ "a 5-bit unsigned immediate") \
Y(IMMEDIATE, imm, "SIMM5", OPD_F_SEXT, F(FLD_imm5), \ Y(IMMEDIATE, imm, "SIMM5", OPD_F_SEXT, F(FLD_imm5), \

365
opcodes/po/opcodes.pot
View File

@ -8,7 +8,7 @@ msgid ""
msgstr "" msgstr ""
"Project-Id-Version: PACKAGE VERSION\n" "Project-Id-Version: PACKAGE VERSION\n"
"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" "Report-Msgid-Bugs-To: bug-binutils@gnu.org\n"
"POT-Creation-Date: 2020-01-18 14:01+0000\n" "POT-Creation-Date: 2020-04-30 13:57+0100\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n" "Language-Team: LANGUAGE <LL@li.org>\n"
@ -17,21 +17,21 @@ msgstr ""
"Content-Type: text/plain; charset=CHARSET\n" "Content-Type: text/plain; charset=CHARSET\n"
"Content-Transfer-Encoding: 8bit\n" "Content-Transfer-Encoding: 8bit\n"
#: aarch64-asm.c:809 #: aarch64-asm.c:820
msgid "specified register cannot be read from" msgid "specified register cannot be read from"
msgstr "" msgstr ""
#: aarch64-asm.c:818 #: aarch64-asm.c:829
msgid "specified register cannot be written to" msgid "specified register cannot be written to"
msgstr "" msgstr ""
#. Invalid option. #. Invalid option.
#: aarch64-dis.c:93 arc-dis.c:801 arm-dis.c:11361 #: aarch64-dis.c:93 arc-dis.c:802 arm-dis.c:11646
#, c-format #, c-format
msgid "unrecognised disassembler option: %s" msgid "unrecognised disassembler option: %s"
msgstr "" msgstr ""
#: aarch64-dis.c:3521 #: aarch64-dis.c:3531
#, c-format #, c-format
msgid "" msgid ""
"\n" "\n"
@ -39,299 +39,299 @@ msgid ""
"with the -M switch (multiple options should be separated by commas):\n" "with the -M switch (multiple options should be separated by commas):\n"
msgstr "" msgstr ""
#: aarch64-dis.c:3525 #: aarch64-dis.c:3535
#, c-format #, c-format
msgid "" msgid ""
"\n" "\n"
" no-aliases Don't print instruction aliases.\n" " no-aliases Don't print instruction aliases.\n"
msgstr "" msgstr ""
#: aarch64-dis.c:3528 #: aarch64-dis.c:3538
#, c-format #, c-format
msgid "" msgid ""
"\n" "\n"
" aliases Do print instruction aliases.\n" " aliases Do print instruction aliases.\n"
msgstr "" msgstr ""
#: aarch64-dis.c:3531 #: aarch64-dis.c:3541
#, c-format #, c-format
msgid "" msgid ""
"\n" "\n"
" no-notes Don't print instruction notes.\n" " no-notes Don't print instruction notes.\n"
msgstr "" msgstr ""
#: aarch64-dis.c:3534 #: aarch64-dis.c:3544
#, c-format #, c-format
msgid "" msgid ""
"\n" "\n"
" notes Do print instruction notes.\n" " notes Do print instruction notes.\n"
msgstr "" msgstr ""
#: aarch64-dis.c:3538 #: aarch64-dis.c:3548
#, c-format #, c-format
msgid "" msgid ""
"\n" "\n"
" debug_dump Temp switch for debug trace.\n" " debug_dump Temp switch for debug trace.\n"
msgstr "" msgstr ""
#: aarch64-dis.c:3542 mips-dis.c:2778 mips-dis.c:2788 mips-dis.c:2791 #: aarch64-dis.c:3552 mips-dis.c:2778 mips-dis.c:2788 mips-dis.c:2791
#: nfp-dis.c:2981 riscv-dis.c:556 #: nfp-dis.c:2981 riscv-dis.c:556
#, c-format #, c-format
msgid "\n" msgid "\n"
msgstr "" msgstr ""
#: aarch64-opc.c:1346 #: aarch64-opc.c:1347
msgid "immediate value" msgid "immediate value"
msgstr "" msgstr ""
#: aarch64-opc.c:1356 #: aarch64-opc.c:1357
msgid "immediate offset" msgid "immediate offset"
msgstr "" msgstr ""
#: aarch64-opc.c:1366 #: aarch64-opc.c:1367
msgid "register number" msgid "register number"
msgstr "" msgstr ""
#: aarch64-opc.c:1376 #: aarch64-opc.c:1377
msgid "register element index" msgid "register element index"
msgstr "" msgstr ""
#: aarch64-opc.c:1386 #: aarch64-opc.c:1387
msgid "shift amount" msgid "shift amount"
msgstr "" msgstr ""
#: aarch64-opc.c:1398 #: aarch64-opc.c:1399
msgid "multiplier" msgid "multiplier"
msgstr "" msgstr ""
#: aarch64-opc.c:1471 #: aarch64-opc.c:1472
msgid "reg pair must start from even reg" msgid "reg pair must start from even reg"
msgstr "" msgstr ""
#: aarch64-opc.c:1477 #: aarch64-opc.c:1478
msgid "reg pair must be contiguous" msgid "reg pair must be contiguous"
msgstr "" msgstr ""
#: aarch64-opc.c:1491 #: aarch64-opc.c:1492
msgid "extraneous register" msgid "extraneous register"
msgstr "" msgstr ""
#: aarch64-opc.c:1497 #: aarch64-opc.c:1498
msgid "missing register" msgid "missing register"
msgstr "" msgstr ""
#: aarch64-opc.c:1508 #: aarch64-opc.c:1509
msgid "stack pointer register expected" msgid "stack pointer register expected"
msgstr "" msgstr ""
#: aarch64-opc.c:1533 #: aarch64-opc.c:1534
msgid "z0-z15 expected" msgid "z0-z15 expected"
msgstr "" msgstr ""
#: aarch64-opc.c:1534 #: aarch64-opc.c:1535
msgid "z0-z7 expected" msgid "z0-z7 expected"
msgstr "" msgstr ""
#: aarch64-opc.c:1560 #: aarch64-opc.c:1561
msgid "invalid register list" msgid "invalid register list"
msgstr "" msgstr ""
#: aarch64-opc.c:1574 #: aarch64-opc.c:1575
msgid "p0-p7 expected" msgid "p0-p7 expected"
msgstr "" msgstr ""
#: aarch64-opc.c:1600 aarch64-opc.c:1608 #: aarch64-opc.c:1601 aarch64-opc.c:1609
msgid "unexpected address writeback" msgid "unexpected address writeback"
msgstr "" msgstr ""
#: aarch64-opc.c:1619 #: aarch64-opc.c:1620
msgid "address writeback expected" msgid "address writeback expected"
msgstr "" msgstr ""
#: aarch64-opc.c:1666 #: aarch64-opc.c:1667
msgid "negative or unaligned offset expected" msgid "negative or unaligned offset expected"
msgstr "" msgstr ""
#: aarch64-opc.c:1723 #: aarch64-opc.c:1724
msgid "invalid register offset" msgid "invalid register offset"
msgstr "" msgstr ""
#: aarch64-opc.c:1745 #: aarch64-opc.c:1746
msgid "invalid post-increment amount" msgid "invalid post-increment amount"
msgstr "" msgstr ""
#: aarch64-opc.c:1761 aarch64-opc.c:2269 #: aarch64-opc.c:1762 aarch64-opc.c:2271
msgid "invalid shift amount" msgid "invalid shift amount"
msgstr "" msgstr ""
#: aarch64-opc.c:1774 #: aarch64-opc.c:1775
msgid "invalid extend/shift operator" msgid "invalid extend/shift operator"
msgstr "" msgstr ""
#: aarch64-opc.c:1820 aarch64-opc.c:2072 aarch64-opc.c:2107 aarch64-opc.c:2126 #: aarch64-opc.c:1821 aarch64-opc.c:2073 aarch64-opc.c:2108 aarch64-opc.c:2127
#: aarch64-opc.c:2134 aarch64-opc.c:2222 aarch64-opc.c:2399 aarch64-opc.c:2499 #: aarch64-opc.c:2135 aarch64-opc.c:2224 aarch64-opc.c:2401 aarch64-opc.c:2501
#: aarch64-opc.c:2512 #: aarch64-opc.c:2514
msgid "immediate out of range" msgid "immediate out of range"
msgstr "" msgstr ""
#: aarch64-opc.c:1842 aarch64-opc.c:1884 aarch64-opc.c:1946 aarch64-opc.c:1980 #: aarch64-opc.c:1843 aarch64-opc.c:1885 aarch64-opc.c:1947 aarch64-opc.c:1981
msgid "invalid addressing mode" msgid "invalid addressing mode"
msgstr "" msgstr ""
#: aarch64-opc.c:1938 #: aarch64-opc.c:1939
msgid "index register xzr is not allowed" msgid "index register xzr is not allowed"
msgstr "" msgstr ""
#: aarch64-opc.c:2060 aarch64-opc.c:2082 aarch64-opc.c:2302 aarch64-opc.c:2310 #: aarch64-opc.c:2061 aarch64-opc.c:2083 aarch64-opc.c:2304 aarch64-opc.c:2312
#: aarch64-opc.c:2376 aarch64-opc.c:2405 #: aarch64-opc.c:2378 aarch64-opc.c:2407
msgid "invalid shift operator" msgid "invalid shift operator"
msgstr "" msgstr ""
#: aarch64-opc.c:2066 #: aarch64-opc.c:2067
msgid "shift amount must be 0 or 12" msgid "shift amount must be 0 or 12"
msgstr "" msgstr ""
#: aarch64-opc.c:2089 #: aarch64-opc.c:2090
msgid "shift amount must be a multiple of 16" msgid "shift amount must be a multiple of 16"
msgstr "" msgstr ""
#: aarch64-opc.c:2101 #: aarch64-opc.c:2102
msgid "negative immediate value not allowed" msgid "negative immediate value not allowed"
msgstr "" msgstr ""
#: aarch64-opc.c:2233 #: aarch64-opc.c:2235
msgid "immediate zero expected" msgid "immediate zero expected"
msgstr "" msgstr ""
#: aarch64-opc.c:2247 #: aarch64-opc.c:2249
msgid "rotate expected to be 0, 90, 180 or 270" msgid "rotate expected to be 0, 90, 180 or 270"
msgstr "" msgstr ""
#: aarch64-opc.c:2258 #: aarch64-opc.c:2260
msgid "rotate expected to be 90 or 270" msgid "rotate expected to be 90 or 270"
msgstr "" msgstr ""
#: aarch64-opc.c:2318 #: aarch64-opc.c:2320
msgid "shift is not permitted" msgid "shift is not permitted"
msgstr "" msgstr ""
#: aarch64-opc.c:2343 #: aarch64-opc.c:2345
msgid "invalid value for immediate" msgid "invalid value for immediate"
msgstr "" msgstr ""
#: aarch64-opc.c:2368 #: aarch64-opc.c:2370
msgid "shift amount must be 0 or 16" msgid "shift amount must be 0 or 16"
msgstr "" msgstr ""
#: aarch64-opc.c:2389 #: aarch64-opc.c:2391
msgid "floating-point immediate expected" msgid "floating-point immediate expected"
msgstr "" msgstr ""
#: aarch64-opc.c:2423 #: aarch64-opc.c:2425
msgid "no shift amount allowed for 8-bit constants" msgid "no shift amount allowed for 8-bit constants"
msgstr "" msgstr ""
#: aarch64-opc.c:2433 #: aarch64-opc.c:2435
msgid "shift amount must be 0 or 8" msgid "shift amount must be 0 or 8"
msgstr "" msgstr ""
#: aarch64-opc.c:2446 #: aarch64-opc.c:2448
msgid "immediate too big for element size" msgid "immediate too big for element size"
msgstr "" msgstr ""
#: aarch64-opc.c:2453 #: aarch64-opc.c:2455
msgid "invalid arithmetic immediate" msgid "invalid arithmetic immediate"
msgstr "" msgstr ""
#: aarch64-opc.c:2467 #: aarch64-opc.c:2469
msgid "floating-point value must be 0.5 or 1.0" msgid "floating-point value must be 0.5 or 1.0"
msgstr "" msgstr ""
#: aarch64-opc.c:2477 #: aarch64-opc.c:2479
msgid "floating-point value must be 0.5 or 2.0" msgid "floating-point value must be 0.5 or 2.0"
msgstr "" msgstr ""
#: aarch64-opc.c:2487 #: aarch64-opc.c:2489
msgid "floating-point value must be 0.0 or 1.0" msgid "floating-point value must be 0.0 or 1.0"
msgstr "" msgstr ""
#: aarch64-opc.c:2518 #: aarch64-opc.c:2520
msgid "invalid replicated MOV immediate" msgid "invalid replicated MOV immediate"
msgstr "" msgstr ""
#: aarch64-opc.c:2639 #: aarch64-opc.c:2641
msgid "extend operator expected" msgid "extend operator expected"
msgstr "" msgstr ""
#: aarch64-opc.c:2652 #: aarch64-opc.c:2654
msgid "missing extend operator" msgid "missing extend operator"
msgstr "" msgstr ""
#: aarch64-opc.c:2658 #: aarch64-opc.c:2660
msgid "'LSL' operator not allowed" msgid "'LSL' operator not allowed"
msgstr "" msgstr ""
#: aarch64-opc.c:2679 #: aarch64-opc.c:2681
msgid "W register expected" msgid "W register expected"
msgstr "" msgstr ""
#: aarch64-opc.c:2690 #: aarch64-opc.c:2692
msgid "shift operator expected" msgid "shift operator expected"
msgstr "" msgstr ""
#: aarch64-opc.c:2697 #: aarch64-opc.c:2699
msgid "'ROR' operator not allowed" msgid "'ROR' operator not allowed"
msgstr "" msgstr ""
#: aarch64-opc.c:3711 #: aarch64-opc.c:3714
msgid "reading from a write-only register" msgid "reading from a write-only register"
msgstr "" msgstr ""
#: aarch64-opc.c:3713 #: aarch64-opc.c:3716
msgid "writing to a read-only register" msgid "writing to a read-only register"
msgstr "" msgstr ""
#: aarch64-opc.c:4880 #: aarch64-opc.c:4886
msgid "instruction opens new dependency sequence without ending previous one" msgid "instruction opens new dependency sequence without ending previous one"
msgstr "" msgstr ""
#: aarch64-opc.c:4900 #: aarch64-opc.c:4906
msgid "previous `movprfx' sequence not closed" msgid "previous `movprfx' sequence not closed"
msgstr "" msgstr ""
#: aarch64-opc.c:4919 #: aarch64-opc.c:4925
msgid "SVE instruction expected after `movprfx'" msgid "SVE instruction expected after `movprfx'"
msgstr "" msgstr ""
#: aarch64-opc.c:4932 #: aarch64-opc.c:4938
msgid "SVE `movprfx' compatible instruction expected" msgid "SVE `movprfx' compatible instruction expected"
msgstr "" msgstr ""
#: aarch64-opc.c:5019 #: aarch64-opc.c:5025
msgid "predicated instruction expected after `movprfx'" msgid "predicated instruction expected after `movprfx'"
msgstr "" msgstr ""
#: aarch64-opc.c:5031 #: aarch64-opc.c:5037
msgid "merging predicate expected due to preceding `movprfx'" msgid "merging predicate expected due to preceding `movprfx'"
msgstr "" msgstr ""
#: aarch64-opc.c:5043 #: aarch64-opc.c:5049
msgid "predicate register differs from that in preceding `movprfx'" msgid "predicate register differs from that in preceding `movprfx'"
msgstr "" msgstr ""
#: aarch64-opc.c:5062 #: aarch64-opc.c:5068
msgid "output register of preceding `movprfx' not used in current instruction" msgid "output register of preceding `movprfx' not used in current instruction"
msgstr "" msgstr ""
#: aarch64-opc.c:5075 #: aarch64-opc.c:5081
msgid "output register of preceding `movprfx' expected as output" msgid "output register of preceding `movprfx' expected as output"
msgstr "" msgstr ""
#: aarch64-opc.c:5087 #: aarch64-opc.c:5093
msgid "output register of preceding `movprfx' used as input" msgid "output register of preceding `movprfx' used as input"
msgstr "" msgstr ""
#: aarch64-opc.c:5103 #: aarch64-opc.c:5109
msgid "register size not compatible with previous `movprfx'" msgid "register size not compatible with previous `movprfx'"
msgstr "" msgstr ""
@ -351,12 +351,16 @@ msgid ""
"\t\t\t\t" "\t\t\t\t"
msgstr "" msgstr ""
#: arc-dis.c:844 #: arc-dis.c:440
msgid "An error occured while generating the extension instruction operations"
msgstr ""
#: arc-dis.c:845
#, c-format #, c-format
msgid "unrecognised disassembler CPU option: %s" msgid "unrecognised disassembler CPU option: %s"
msgstr "" msgstr ""
#: arc-dis.c:1411 #: arc-dis.c:1412
#, c-format #, c-format
msgid "" msgid ""
"\n" "\n"
@ -364,47 +368,47 @@ msgid ""
"with -M switch (multiple options should be separated by commas):\n" "with -M switch (multiple options should be separated by commas):\n"
msgstr "" msgstr ""
#: arc-dis.c:1423 #: arc-dis.c:1424
#, c-format #, c-format
msgid " dsp Recognize DSP instructions.\n" msgid " dsp Recognize DSP instructions.\n"
msgstr "" msgstr ""
#: arc-dis.c:1425 #: arc-dis.c:1426
#, c-format #, c-format
msgid " spfp Recognize FPX SP instructions.\n" msgid " spfp Recognize FPX SP instructions.\n"
msgstr "" msgstr ""
#: arc-dis.c:1427 #: arc-dis.c:1428
#, c-format #, c-format
msgid " dpfp Recognize FPX DP instructions.\n" msgid " dpfp Recognize FPX DP instructions.\n"
msgstr "" msgstr ""
#: arc-dis.c:1429 #: arc-dis.c:1430
#, c-format #, c-format
msgid " quarkse_em Recognize FPU QuarkSE-EM instructions.\n" msgid " quarkse_em Recognize FPU QuarkSE-EM instructions.\n"
msgstr "" msgstr ""
#: arc-dis.c:1431 #: arc-dis.c:1432
#, c-format #, c-format
msgid " fpuda Recognize double assist FPU instructions.\n" msgid " fpuda Recognize double assist FPU instructions.\n"
msgstr "" msgstr ""
#: arc-dis.c:1433 #: arc-dis.c:1434
#, c-format #, c-format
msgid " fpus Recognize single precision FPU instructions.\n" msgid " fpus Recognize single precision FPU instructions.\n"
msgstr "" msgstr ""
#: arc-dis.c:1435 #: arc-dis.c:1436
#, c-format #, c-format
msgid " fpud Recognize double precision FPU instructions.\n" msgid " fpud Recognize double precision FPU instructions.\n"
msgstr "" msgstr ""
#: arc-dis.c:1437 #: arc-dis.c:1438
#, c-format #, c-format
msgid " nps400 Recognize NPS400 instructions.\n" msgid " nps400 Recognize NPS400 instructions.\n"
msgstr "" msgstr ""
#: arc-dis.c:1439 #: arc-dis.c:1440
#, c-format #, c-format
msgid " hex Use only hexadecimal number to print immediates.\n" msgid " hex Use only hexadecimal number to print immediates.\n"
msgstr "" msgstr ""
@ -570,48 +574,67 @@ msgstr ""
msgid "invalid position, should be one of: 0,4,8,...124." msgid "invalid position, should be one of: 0,4,8,...124."
msgstr "" msgstr ""
#: arm-dis.c:5105 #: arm-dis.c:5184
msgid "Select raw register names" msgid "Select raw register names"
msgstr "" msgstr ""
#: arm-dis.c:5107 #: arm-dis.c:5186
msgid "Select register names used by GCC" msgid "Select register names used by GCC"
msgstr "" msgstr ""
#: arm-dis.c:5109 #: arm-dis.c:5188
msgid "Select register names used in ARM's ISA documentation" msgid "Select register names used in ARM's ISA documentation"
msgstr "" msgstr ""
#: arm-dis.c:5111 #: arm-dis.c:5190
msgid "Assume all insns are Thumb insns" msgid "Assume all insns are Thumb insns"
msgstr "" msgstr ""
#: arm-dis.c:5112 #: arm-dis.c:5191
msgid "Examine preceding label to determine an insn's type" msgid "Examine preceding label to determine an insn's type"
msgstr "" msgstr ""
#: arm-dis.c:5113 #: arm-dis.c:5192
msgid "Select register names used in the APCS" msgid "Select register names used in the APCS"
msgstr "" msgstr ""
#: arm-dis.c:5115 #: arm-dis.c:5194
msgid "Select register names used in the ATPCS" msgid "Select register names used in the ATPCS"
msgstr "" msgstr ""
#: arm-dis.c:5117 #: arm-dis.c:5196
msgid "Select special register names used in the ATPCS" msgid "Select special register names used in the ATPCS"
msgstr "" msgstr ""
#: arm-dis.c:8286 #: arm-dis.c:5198
msgid "Enable CDE extensions for coprocessor N space"
msgstr ""
#: arm-dis.c:8367
msgid "<illegal precision>" msgid "<illegal precision>"
msgstr "" msgstr ""
#: arm-dis.c:11352 #: arm-dis.c:11607
#, c-format #, c-format
msgid "unrecognised register name set: %s" msgid "unrecognised register name set: %s"
msgstr "" msgstr ""
#: arm-dis.c:12066 #: arm-dis.c:11621
#, c-format
msgid "cde coprocessor not between 0-7: %s"
msgstr ""
#: arm-dis.c:11627
#, c-format
msgid "coproc must have an argument: %s"
msgstr ""
#: arm-dis.c:11640
#, c-format
msgid "coprocN argument takes options \"generic\", \"cde\", or \"CDE\": %s"
msgstr ""
#: arm-dis.c:12351
#, c-format #, c-format
msgid "" msgid ""
"\n" "\n"
@ -716,19 +739,19 @@ msgstr ""
msgid "bad instruction `%.50s'" msgid "bad instruction `%.50s'"
msgstr "" msgstr ""
#: bpf-desc.c:1441 #: bpf-desc.c:1661
#, c-format #, c-format
msgid "" msgid ""
"internal error: bpf_cgen_rebuild_tables: conflicting insn-chunk-bitsize " "internal error: bpf_cgen_rebuild_tables: conflicting insn-chunk-bitsize "
"values: `%d' vs. `%d'" "values: `%d' vs. `%d'"
msgstr "" msgstr ""
#: bpf-desc.c:1524 #: bpf-desc.c:1744
#, c-format #, c-format
msgid "internal error: bpf_cgen_cpu_open: unsupported argument `%d'" msgid "internal error: bpf_cgen_cpu_open: unsupported argument `%d'"
msgstr "" msgstr ""
#: bpf-desc.c:1543 #: bpf-desc.c:1763
#, c-format #, c-format
msgid "internal error: bpf_cgen_cpu_open: no endianness specified" msgid "internal error: bpf_cgen_cpu_open: no endianness specified"
msgstr "" msgstr ""
@ -772,50 +795,50 @@ msgstr ""
msgid "operand out of range (%ld not between %ld and %ld)" msgid "operand out of range (%ld not between %ld and %ld)"
msgstr "" msgstr ""
#: bpf-ibld.c:625 epiphany-ibld.c:880 fr30-ibld.c:735 frv-ibld.c:861 #: bpf-ibld.c:628 epiphany-ibld.c:883 fr30-ibld.c:738 frv-ibld.c:864
#: ip2k-ibld.c:612 iq2000-ibld.c:718 lm32-ibld.c:639 m32c-ibld.c:1736 #: ip2k-ibld.c:615 iq2000-ibld.c:721 lm32-ibld.c:642 m32c-ibld.c:1739
#: m32r-ibld.c:670 mep-ibld.c:1213 mt-ibld.c:754 or1k-ibld.c:742 #: m32r-ibld.c:673 mep-ibld.c:1216 mt-ibld.c:757 or1k-ibld.c:745
#: xc16x-ibld.c:757 xstormy16-ibld.c:683 #: xc16x-ibld.c:760 xstormy16-ibld.c:686
#, c-format #, c-format
msgid "internal error: unrecognized field %d while building insn" msgid "internal error: unrecognized field %d while building insn"
msgstr "" msgstr ""
#: bpf-ibld.c:709 epiphany-ibld.c:1175 fr30-ibld.c:941 frv-ibld.c:1179 #: bpf-ibld.c:712 epiphany-ibld.c:1178 fr30-ibld.c:944 frv-ibld.c:1182
#: ip2k-ibld.c:688 iq2000-ibld.c:894 lm32-ibld.c:744 m32c-ibld.c:2898 #: ip2k-ibld.c:691 iq2000-ibld.c:897 lm32-ibld.c:747 m32c-ibld.c:2901
#: m32r-ibld.c:808 mep-ibld.c:1813 mt-ibld.c:975 or1k-ibld.c:910 #: m32r-ibld.c:811 mep-ibld.c:1816 mt-ibld.c:978 or1k-ibld.c:913
#: xc16x-ibld.c:978 xstormy16-ibld.c:830 #: xc16x-ibld.c:981 xstormy16-ibld.c:833
#, c-format #, c-format
msgid "internal error: unrecognized field %d while decoding insn" msgid "internal error: unrecognized field %d while decoding insn"
msgstr "" msgstr ""
#: bpf-ibld.c:778 epiphany-ibld.c:1319 fr30-ibld.c:1088 frv-ibld.c:1458 #: bpf-ibld.c:781 epiphany-ibld.c:1322 fr30-ibld.c:1091 frv-ibld.c:1461
#: ip2k-ibld.c:763 iq2000-ibld.c:1026 lm32-ibld.c:834 m32c-ibld.c:3516 #: ip2k-ibld.c:766 iq2000-ibld.c:1029 lm32-ibld.c:837 m32c-ibld.c:3519
#: m32r-ibld.c:922 mep-ibld.c:2284 mt-ibld.c:1176 or1k-ibld.c:1015 #: m32r-ibld.c:925 mep-ibld.c:2287 mt-ibld.c:1179 or1k-ibld.c:1018
#: xc16x-ibld.c:1200 xstormy16-ibld.c:941 #: xc16x-ibld.c:1203 xstormy16-ibld.c:944
#, c-format #, c-format
msgid "internal error: unrecognized field %d while getting int operand" msgid "internal error: unrecognized field %d while getting int operand"
msgstr "" msgstr ""
#: bpf-ibld.c:829 epiphany-ibld.c:1445 fr30-ibld.c:1217 frv-ibld.c:1719 #: bpf-ibld.c:832 epiphany-ibld.c:1448 fr30-ibld.c:1220 frv-ibld.c:1722
#: ip2k-ibld.c:820 iq2000-ibld.c:1140 lm32-ibld.c:906 m32c-ibld.c:4116 #: ip2k-ibld.c:823 iq2000-ibld.c:1143 lm32-ibld.c:909 m32c-ibld.c:4119
#: m32r-ibld.c:1018 mep-ibld.c:2737 mt-ibld.c:1359 or1k-ibld.c:1102 #: m32r-ibld.c:1021 mep-ibld.c:2740 mt-ibld.c:1362 or1k-ibld.c:1105
#: xc16x-ibld.c:1404 xstormy16-ibld.c:1034 #: xc16x-ibld.c:1407 xstormy16-ibld.c:1037
#, c-format #, c-format
msgid "internal error: unrecognized field %d while getting vma operand" msgid "internal error: unrecognized field %d while getting vma operand"
msgstr "" msgstr ""
#: bpf-ibld.c:887 epiphany-ibld.c:1578 fr30-ibld.c:1349 frv-ibld.c:1987 #: bpf-ibld.c:890 epiphany-ibld.c:1581 fr30-ibld.c:1352 frv-ibld.c:1990
#: ip2k-ibld.c:880 iq2000-ibld.c:1261 lm32-ibld.c:985 m32c-ibld.c:4704 #: ip2k-ibld.c:883 iq2000-ibld.c:1264 lm32-ibld.c:988 m32c-ibld.c:4707
#: m32r-ibld.c:1120 mep-ibld.c:3151 mt-ibld.c:1549 or1k-ibld.c:1196 #: m32r-ibld.c:1123 mep-ibld.c:3154 mt-ibld.c:1552 or1k-ibld.c:1199
#: xc16x-ibld.c:1609 xstormy16-ibld.c:1134 #: xc16x-ibld.c:1612 xstormy16-ibld.c:1137
#, c-format #, c-format
msgid "internal error: unrecognized field %d while setting int operand" msgid "internal error: unrecognized field %d while setting int operand"
msgstr "" msgstr ""
#: bpf-ibld.c:935 epiphany-ibld.c:1701 fr30-ibld.c:1471 frv-ibld.c:2245 #: bpf-ibld.c:938 epiphany-ibld.c:1704 fr30-ibld.c:1474 frv-ibld.c:2248
#: ip2k-ibld.c:930 iq2000-ibld.c:1372 lm32-ibld.c:1054 m32c-ibld.c:5282 #: ip2k-ibld.c:933 iq2000-ibld.c:1375 lm32-ibld.c:1057 m32c-ibld.c:5285
#: m32r-ibld.c:1212 mep-ibld.c:3555 mt-ibld.c:1729 or1k-ibld.c:1280 #: m32r-ibld.c:1215 mep-ibld.c:3558 mt-ibld.c:1732 or1k-ibld.c:1283
#: xc16x-ibld.c:1804 xstormy16-ibld.c:1224 #: xc16x-ibld.c:1807 xstormy16-ibld.c:1227
#, c-format #, c-format
msgid "internal error: unrecognized field %d while setting vma operand" msgid "internal error: unrecognized field %d while setting vma operand"
msgstr "" msgstr ""
@ -846,6 +869,15 @@ msgstr ""
msgid "Address 0x%s is out of bounds.\n" msgid "Address 0x%s is out of bounds.\n"
msgstr "" msgstr ""
#: disassemble.c:839
#, c-format
msgid "assertion fail %s:%d"
msgstr ""
#: disassemble.c:840
msgid "Please report this bug"
msgstr ""
#: epiphany-asm.c:68 #: epiphany-asm.c:68
msgid "register unavailable for short instructions" msgid "register unavailable for short instructions"
msgstr "" msgstr ""
@ -979,26 +1011,21 @@ msgstr ""
msgid "internal error: bad insn unit" msgid "internal error: bad insn unit"
msgstr "" msgstr ""
#: h8300-dis.c:63 #: h8300-dis.c:309
#, c-format
msgid "internal error, h8_disassemble_init"
msgstr ""
#: h8300-dis.c:315
#, c-format #, c-format
msgid "Hmmmm 0x%x" msgid "Hmmmm 0x%x"
msgstr "" msgstr ""
#: h8300-dis.c:692 #: h8300-dis.c:617
#, c-format #, c-format
msgid "Don't understand 0x%x \n" msgid "Don't understand 0x%x \n"
msgstr "" msgstr ""
#: i386-dis.c:11062 #: i386-dis.c:11091
msgid "<internal disassembler error>" msgid "<internal disassembler error>"
msgstr "" msgstr ""
#: i386-dis.c:11360 #: i386-dis.c:11389
#, c-format #, c-format
msgid "" msgid ""
"\n" "\n"
@ -1007,145 +1034,145 @@ msgid ""
"with the -M switch (multiple options should be separated by commas):\n" "with the -M switch (multiple options should be separated by commas):\n"
msgstr "" msgstr ""
#: i386-dis.c:11364 #: i386-dis.c:11393
#, c-format #, c-format
msgid " x86-64 Disassemble in 64bit mode\n" msgid " x86-64 Disassemble in 64bit mode\n"
msgstr "" msgstr ""
#: i386-dis.c:11365 #: i386-dis.c:11394
#, c-format #, c-format
msgid " i386 Disassemble in 32bit mode\n" msgid " i386 Disassemble in 32bit mode\n"
msgstr "" msgstr ""
#: i386-dis.c:11366 #: i386-dis.c:11395
#, c-format #, c-format
msgid " i8086 Disassemble in 16bit mode\n" msgid " i8086 Disassemble in 16bit mode\n"
msgstr "" msgstr ""
#: i386-dis.c:11367 #: i386-dis.c:11396
#, c-format #, c-format
msgid " att Display instruction in AT&T syntax\n" msgid " att Display instruction in AT&T syntax\n"
msgstr "" msgstr ""
#: i386-dis.c:11368 #: i386-dis.c:11397
#, c-format #, c-format
msgid " intel Display instruction in Intel syntax\n" msgid " intel Display instruction in Intel syntax\n"
msgstr "" msgstr ""
#: i386-dis.c:11369 #: i386-dis.c:11398
#, c-format #, c-format
msgid "" msgid ""
" att-mnemonic\n" " att-mnemonic\n"
" Display instruction in AT&T mnemonic\n" " Display instruction in AT&T mnemonic\n"
msgstr "" msgstr ""
#: i386-dis.c:11371 #: i386-dis.c:11400
#, c-format #, c-format
msgid "" msgid ""
" intel-mnemonic\n" " intel-mnemonic\n"
" Display instruction in Intel mnemonic\n" " Display instruction in Intel mnemonic\n"
msgstr "" msgstr ""
#: i386-dis.c:11373 #: i386-dis.c:11402
#, c-format #, c-format
msgid " addr64 Assume 64bit address size\n" msgid " addr64 Assume 64bit address size\n"
msgstr "" msgstr ""
#: i386-dis.c:11374 #: i386-dis.c:11403
#, c-format #, c-format
msgid " addr32 Assume 32bit address size\n" msgid " addr32 Assume 32bit address size\n"
msgstr "" msgstr ""
#: i386-dis.c:11375 #: i386-dis.c:11404
#, c-format #, c-format
msgid " addr16 Assume 16bit address size\n" msgid " addr16 Assume 16bit address size\n"
msgstr "" msgstr ""
#: i386-dis.c:11376 #: i386-dis.c:11405
#, c-format #, c-format
msgid " data32 Assume 32bit data size\n" msgid " data32 Assume 32bit data size\n"
msgstr "" msgstr ""
#: i386-dis.c:11377 #: i386-dis.c:11406
#, c-format #, c-format
msgid " data16 Assume 16bit data size\n" msgid " data16 Assume 16bit data size\n"
msgstr "" msgstr ""
#: i386-dis.c:11378 #: i386-dis.c:11407
#, c-format #, c-format
msgid " suffix Always display instruction suffix in AT&T syntax\n" msgid " suffix Always display instruction suffix in AT&T syntax\n"
msgstr "" msgstr ""
#: i386-dis.c:11379 #: i386-dis.c:11408
#, c-format #, c-format
msgid " amd64 Display instruction in AMD64 ISA\n" msgid " amd64 Display instruction in AMD64 ISA\n"
msgstr "" msgstr ""
#: i386-dis.c:11380 #: i386-dis.c:11409
#, c-format #, c-format
msgid " intel64 Display instruction in Intel64 ISA\n" msgid " intel64 Display instruction in Intel64 ISA\n"
msgstr "" msgstr ""
#: i386-dis.c:11943 #: i386-dis.c:11972
msgid "64-bit address is disabled" msgid "64-bit address is disabled"
msgstr "" msgstr ""
#: i386-gen.c:754 #: i386-gen.c:792
#, c-format #, c-format
msgid "%s: error: " msgid "%s: error: "
msgstr "" msgstr ""
#: i386-gen.c:917 #: i386-gen.c:959
#, c-format #, c-format
msgid "%s: %d: unknown bitfield: %s\n" msgid "%s: %d: unknown bitfield: %s\n"
msgstr "" msgstr ""
#: i386-gen.c:919 #: i386-gen.c:961
#, c-format #, c-format
msgid "unknown bitfield: %s\n" msgid "unknown bitfield: %s\n"
msgstr "" msgstr ""
#: i386-gen.c:982 #: i386-gen.c:1024
#, c-format #, c-format
msgid "%s: %d: missing `)' in bitfield: %s\n" msgid "%s: %d: missing `)' in bitfield: %s\n"
msgstr "" msgstr ""
#: i386-gen.c:1083 #: i386-gen.c:1125
#, c-format #, c-format
msgid "unknown broadcast operand: %s\n" msgid "unknown broadcast operand: %s\n"
msgstr "" msgstr ""
#: i386-gen.c:1538 #: i386-gen.c:1776
#, c-format #, c-format
msgid "can't find i386-reg.tbl for reading, errno = %s\n" msgid "can't find i386-reg.tbl for reading, errno = %s\n"
msgstr "" msgstr ""
#: i386-gen.c:1616 #: i386-gen.c:1854
#, c-format #, c-format
msgid "can't create i386-init.h, errno = %s\n" msgid "can't create i386-init.h, errno = %s\n"
msgstr "" msgstr ""
#: i386-gen.c:1706 ia64-gen.c:2829 #: i386-gen.c:1944 ia64-gen.c:2829
#, c-format #, c-format
msgid "unable to change directory to \"%s\", errno = %s\n" msgid "unable to change directory to \"%s\", errno = %s\n"
msgstr "" msgstr ""
#: i386-gen.c:1720 i386-gen.c:1725 #: i386-gen.c:1958 i386-gen.c:1963
#, c-format #, c-format
msgid "CpuMax != %d!\n" msgid "CpuMax != %d!\n"
msgstr "" msgstr ""
#: i386-gen.c:1729 #: i386-gen.c:1967
#, c-format #, c-format
msgid "%d unused bits in i386_cpu_flags.\n" msgid "%d unused bits in i386_cpu_flags.\n"
msgstr "" msgstr ""
#: i386-gen.c:1744 #: i386-gen.c:1982
#, c-format #, c-format
msgid "%d unused bits in i386_operand_type.\n" msgid "%d unused bits in i386_operand_type.\n"
msgstr "" msgstr ""
#: i386-gen.c:1758 #: i386-gen.c:1996
#, c-format #, c-format
msgid "can't create i386-tbl.h, errno = %s\n" msgid "can't create i386-tbl.h, errno = %s\n"
msgstr "" msgstr ""
@ -1765,6 +1792,10 @@ msgstr ""
msgid "internal error: unknown hardware resource" msgid "internal error: unknown hardware resource"
msgstr "" msgstr ""
#: nds32-dis.c:1186
msgid "insufficient data to decode instruction"
msgstr ""
#: nfp-dis.c:927 #: nfp-dis.c:927
msgid "<invalid_instruction>:" msgid "<invalid_instruction>:"
msgstr "" msgstr ""
@ -1872,7 +1903,7 @@ msgstr ""
msgid "warning: ignoring unknown -M%s option" msgid "warning: ignoring unknown -M%s option"
msgstr "" msgstr ""
#: ppc-dis.c:957 #: ppc-dis.c:965
#, c-format #, c-format
msgid "" msgid ""
"\n" "\n"
@ -2041,15 +2072,15 @@ msgstr ""
msgid "<invalid size>" msgid "<invalid size>"
msgstr "" msgstr ""
#: s12z-dis.c:258 s12z-dis.c:315 s12z-dis.c:326 #: s12z-dis.c:251 s12z-dis.c:308 s12z-dis.c:319
msgid "<illegal reg num>" msgid "<illegal reg num>"
msgstr "" msgstr ""
#: s12z-dis.c:389 #: s12z-dis.c:382
msgid "<bad>" msgid "<bad>"
msgstr "" msgstr ""
#: s12z-dis.c:400 #: s12z-dis.c:392
msgid ".<bad>" msgid ".<bad>"
msgstr "" msgstr ""