mirror of
https://github.com/espressif/binutils-gdb.git
synced 2025-06-01 20:12:01 +08:00
2011-01-07 Michael Snyder <msnyder@vmware.com>
* ada-lang.c: Comment cleanup, mostly periods and spaces. * ada-lang.h: Ditto. * ada-tasks.c: Ditto. * ada-valprint.c: Ditto. * aix-threads.c: Ditto. * alpha-linux-nat.c: Ditto. * alpha-linux-tdep.c: Ditto. * alpha-mdebug-tdep.c: Ditto. * alpha-nat.c: Ditto. * alpha-osf1-tdep.c: Ditto. * alpha-tdep.c: Ditto. * alphabsd-nat.c: Ditto. * alphabsd-tdep.c: Ditto. * amd64-darwin-tdep.c: Ditto. * amd64-linux-nat.c: Ditto. * amd64-linux-tdep.c: Ditto. * amd64-sol2-tdep.c: Ditto. * amd64-tdep.c: Ditto. * amd64-fbsd-tdep.c: Ditto. * amd64-nbsd-tdep.c: Ditto. * amd64-obsd-tdep.c: Ditto. * amd64-linux-nat.c: Ditto. * amd64-linux-tdep.c: Ditto. * arm-tdep.c: Ditto. * arm-tdep.h: Ditto. * armnbsd-nat.c: Ditto. * avr-tdep.c: Ditto. * bfin-tdep.c: Ditto. * bsd-kvm.c: Ditto. * c-typeprintc: Ditto. * c-valprint.c: Ditto. * coff-pe-read.h: Ditto. * coffreead.c: Ditto. * cris-tdep.c: Ditto. * d-lang.c: Ditto. * darwin-nat-info.c: Ditto. * darwin-nat.c: Ditto. * dbug-rom.c: Ditto. * dbxread.c: Ditto. * dcache.c: Ditto. * dcache.h: Ditto. * dec-thread.c: Ditto. * defs.h: Ditto. * demangle.c: Ditto. * dicos-tdep.c: Ditto. * dictionary.c: Ditto. * dictionary.h: Ditto. * dink32-rom.c: Ditto. * disasm.c: Ditto. * doublest.c: Ditto. * dsrec.c: Ditto. * dummy-frame.c: Ditto. * dwarf2-frame.c: Ditto. * dwarf2expr.c: Ditto. * dwarf2loc.c: Ditto. * dwarf2read.c: Ditto. * elfread.c: Ditto. * environ.c: Ditto. * eval.c: Ditto. * event-top.h: Ditto. * exceptions.c: Ditto. * exceptions.h: Ditto. * exec.c: Ditto. * expprint.c: Ditto. * expression.h: Ditto. * f-exp.y: Ditto. * f-lang.c: Ditto. * f-lang.h: Ditto. * f-typeprint.c: Ditto. * f-valprint.c: Ditto. * fbsd-nat.c: Ditto. * findvar.c: Ditto. * fork-child.c: Ditto. * frame.c: Ditto. * frame.h: Ditto. * frv-linux-tdep.c: Ditto. * frv-tdep.c: Ditto. * gcore.c: Ditto. * gdb-stabs.h: Ditto. * gdb_assert.h: Ditto. * gdb_string.h: Ditto. * gdb_thread_db.h: Ditto. * gdb_wait.h: Ditto. * gdbarch.sh: Ditto. * gdbcore.h: Ditto. * gdbthread.h: Ditto. * gdbtypes.c: Ditto. * gdbtypes.h: Ditto. * gnu-nat.c: Ditto. * gnu-nat.h: Ditto. * gnu-v2-abi.c: Ditto. * gnu-v3-abi.c: Ditto. * go32-nat.c: Ditto. * gdbarch.c: Regenerate. * gdbarch.h: Regenerate.
This commit is contained in:
Michael Snyder
158
gdb/arm-tdep.c
158
gdb/arm-tdep.c
@ -19,7 +19,7 @@
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include <ctype.h> /* XXX for isupper () */
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#include <ctype.h> /* XXX for isupper (). */
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#include "defs.h"
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#include "frame.h"
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@ -27,7 +27,7 @@
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#include "gdbcmd.h"
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#include "gdbcore.h"
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#include "gdb_string.h"
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#include "dis-asm.h" /* For register styles. */
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#include "dis-asm.h" /* For register styles. */
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#include "regcache.h"
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#include "reggroups.h"
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#include "doublest.h"
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@ -65,7 +65,7 @@ static int arm_debug;
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MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
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MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
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#define MSYMBOL_SET_SPECIAL(msym) \
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#define MSYMBOL_SET_SPECIAL(msym) \
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MSYMBOL_TARGET_FLAG_1 (msym) = 1
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#define MSYMBOL_IS_SPECIAL(msym) \
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@ -845,7 +845,8 @@ thumb_analyze_prologue (struct gdbarch *gdbarch,
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break;
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}
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else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!}, { registers } */
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else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!},
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{ registers } */
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&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
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{
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pv_t addr = regs[bits (insn, 0, 3)];
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@ -866,7 +867,8 @@ thumb_analyze_prologue (struct gdbarch *gdbarch,
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regs[bits (insn, 0, 3)] = addr;
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}
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else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2, [Rn, #+/-imm]{!} */
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else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2,
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[Rn, #+/-imm]{!} */
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&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
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{
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int regno1 = bits (inst2, 12, 15);
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@ -938,14 +940,16 @@ thumb_analyze_prologue (struct gdbarch *gdbarch,
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/* Ignore stores of argument registers to the stack. */
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;
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else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!], { registers } */
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else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!],
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{ registers } */
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&& (inst2 & 0x8000) == 0x0000
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&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
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/* Ignore block loads from the stack, potentially copying
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parameters from memory. */
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;
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else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2, [Rn, #+/-imm] */
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else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
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[Rn, #+/-imm] */
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&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
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/* Similarly ignore dual loads from the stack. */
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;
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@ -1223,8 +1227,8 @@ arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch,
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}
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/* Try to skip a sequence of instructions used for stack protector. If PC
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points to the first instruction of this sequence, return the address of first
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instruction after this sequence, otherwise, return original PC.
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points to the first instruction of this sequence, return the address of
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first instruction after this sequence, otherwise, return original PC.
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On arm, this sequence of instructions is composed of mainly three steps,
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Step 1: load symbol __stack_chk_guard,
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@ -1338,7 +1342,7 @@ arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
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[stfe f6, [sp, #-12]!]
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[stfe f5, [sp, #-12]!]
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[stfe f4, [sp, #-12]!]
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sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
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sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
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static CORE_ADDR
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arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
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@ -1408,7 +1412,7 @@ arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
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/* Find an upper limit on the function prologue using the debug
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information. If the debug information could not be used to provide
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that bound, then use an arbitrary large number as the upper bound. */
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/* Like arm_scan_prologue, stop no later than pc + 64. */
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/* Like arm_scan_prologue, stop no later than pc + 64. */
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limit_pc = skip_prologue_using_sal (gdbarch, pc);
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if (limit_pc == 0)
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limit_pc = pc + 64; /* Magic. */
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@ -1475,7 +1479,7 @@ arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
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break;
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}
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return skip_pc; /* End of prologue */
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return skip_pc; /* End of prologue. */
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}
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/* *INDENT-OFF* */
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@ -1494,7 +1498,7 @@ arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
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R7 -> 0 local variables (16 bytes)
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SP -> -12 additional stack space (12 bytes)
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The frame size would thus be 36 bytes, and the frame offset would be
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12 bytes. The frame register is R7.
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12 bytes. The frame register is R7.
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The comments for thumb_skip_prolog() describe the algorithm we use
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to detect the end of the prolog. */
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@ -1692,7 +1696,8 @@ arm_analyze_prologue (struct gdbarch *gdbarch,
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regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm);
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continue;
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}
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else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd, [sp, #-4]! */
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else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd,
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[sp, #-4]! */
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{
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if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
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break;
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@ -1715,7 +1720,8 @@ arm_analyze_prologue (struct gdbarch *gdbarch,
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for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
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if (mask & (1 << regno))
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{
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regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
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regs[ARM_SP_REGNUM]
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= pv_add_constant (regs[ARM_SP_REGNUM], -4);
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pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
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}
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}
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@ -1733,7 +1739,8 @@ arm_analyze_prologue (struct gdbarch *gdbarch,
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/* No need to add this to saved_regs -- it's just an arg reg. */
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continue;
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}
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else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn, { registers } */
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else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn,
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{ registers } */
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&& pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM))
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{
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/* No need to add this to saved_regs -- it's just arg regs. */
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@ -1753,7 +1760,8 @@ arm_analyze_prologue (struct gdbarch *gdbarch,
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imm = (imm >> rot) | (imm << (32 - rot));
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regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
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}
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else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
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else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?,
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[sp, -#c]! */
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&& gdbarch_tdep (gdbarch)->have_fpa_registers)
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{
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if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
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@ -1763,7 +1771,8 @@ arm_analyze_prologue (struct gdbarch *gdbarch,
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regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
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pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
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}
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else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
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else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
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[sp!] */
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&& gdbarch_tdep (gdbarch)->have_fpa_registers)
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{
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int n_saved_fp_regs;
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@ -1809,7 +1818,7 @@ arm_analyze_prologue (struct gdbarch *gdbarch,
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break;
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}
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else if ((insn & 0xf0000000) != 0xe0000000)
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break; /* Condition not true, exit early */
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break; /* Condition not true, exit early. */
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else if (arm_instruction_changes_pc (insn))
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/* Don't scan past anything that might change control flow. */
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break;
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@ -2186,7 +2195,8 @@ struct frame_base arm_normal_base = {
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static struct frame_id
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arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
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{
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return frame_id_build (get_frame_register_unsigned (this_frame, ARM_SP_REGNUM),
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return frame_id_build (get_frame_register_unsigned (this_frame,
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ARM_SP_REGNUM),
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get_frame_pc (this_frame));
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}
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@ -2355,7 +2365,7 @@ thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
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exception of return itself, updates the stack pointer, we need to
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scan backwards for at most one instruction. Try either a 16-bit or
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a 32-bit instruction. This is just a heuristic, so we do not worry
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too much about false positives.*/
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too much about false positives. */
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if (!found_stack_adjust)
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{
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@ -3396,7 +3406,7 @@ bitcount (unsigned long val)
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{
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int nbits;
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for (nbits = 0; val != 0; nbits++)
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val &= val - 1; /* delete rightmost 1-bit in val */
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val &= val - 1; /* Delete rightmost 1-bit in val. */
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return nbits;
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}
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@ -3441,7 +3451,7 @@ thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc, int insert_bkpt)
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enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
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unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
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unsigned short inst1;
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CORE_ADDR nextpc = pc + 2; /* default is next instruction */
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CORE_ADDR nextpc = pc + 2; /* Default is next instruction. */
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unsigned long offset;
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ULONGEST status, itstate;
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@ -3481,7 +3491,8 @@ thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc, int insert_bkpt)
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while (itstate != 0 && ! condition_true (itstate >> 4, status))
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{
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inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
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inst1 = read_memory_unsigned_integer (pc, 2,
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byte_order_for_code);
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pc += thumb_insn_size (inst1);
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itstate = thumb_advance_itstate (itstate);
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}
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@ -3499,7 +3510,8 @@ thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc, int insert_bkpt)
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while (itstate != 0 && ! condition_true (itstate >> 4, status))
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{
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inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
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inst1 = read_memory_unsigned_integer (pc, 2,
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byte_order_for_code);
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pc += thumb_insn_size (inst1);
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itstate = thumb_advance_itstate (itstate);
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}
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@ -3540,7 +3552,8 @@ thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc, int insert_bkpt)
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the instruction after the IT block. */
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do
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{
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inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
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inst1 = read_memory_unsigned_integer (pc, 2,
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byte_order_for_code);
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pc += thumb_insn_size (inst1);
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itstate = thumb_advance_itstate (itstate);
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}
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@ -3807,8 +3820,8 @@ thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc, int insert_bkpt)
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The value returned has the execution state of the next instruction
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encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
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in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
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address.
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*/
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address. */
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static CORE_ADDR
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arm_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc, int insert_bkpt)
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{
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@ -3879,7 +3892,7 @@ arm_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc, int insert_bkpt)
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return nextpc;
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}
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|
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/* Multiply into PC */
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/* Multiply into PC. */
|
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c = (status & FLAG_C) ? 1 : 0;
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rn = bits (this_instr, 16, 19);
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operand1 = (rn == 15) ? pc_val + 8
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@ -3892,8 +3905,9 @@ arm_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc, int insert_bkpt)
|
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operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
|
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& 0xffffffff;
|
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}
|
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else /* operand 2 is a shifted register */
|
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operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status);
|
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else /* operand 2 is a shifted register. */
|
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operand2 = shifted_reg_val (frame, this_instr, c,
|
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pc_val, status);
|
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|
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switch (bits (this_instr, 21, 24))
|
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{
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@ -4235,7 +4249,8 @@ arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
|
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known boundary. */
|
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if (! definite)
|
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{
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buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary);
|
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buf = extend_buffer_earlier (buf, bpaddr, buf_len,
|
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bpaddr - boundary);
|
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if (buf == NULL)
|
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return bpaddr;
|
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buf_len = bpaddr - boundary;
|
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@ -4296,7 +4311,7 @@ arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
|
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arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
|
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Depending on the type of instruction, it is then copied to a scratch
|
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location, possibly in a modified form. The copy_* set of functions
|
||||
performs such modification, as necessary. A breakpoint is placed after
|
||||
performs such modification, as necessary. A breakpoint is placed after
|
||||
the modified instruction in the scratch space to return control to GDB.
|
||||
Note in particular that instructions which modify the PC will no longer
|
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do so after modification.
|
||||
@ -4358,9 +4373,11 @@ branch_write_pc (struct regcache *regs, ULONGEST val)
|
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if (displaced_in_arm_mode (regs))
|
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/* Note: If bits 0/1 are set, this branch would be unpredictable for
|
||||
architecture versions < 6. */
|
||||
regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & ~(ULONGEST) 0x3);
|
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regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
|
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val & ~(ULONGEST) 0x3);
|
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else
|
||||
regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & ~(ULONGEST) 0x1);
|
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regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM,
|
||||
val & ~(ULONGEST) 0x1);
|
||||
}
|
||||
|
||||
/* Write to the PC as from a branch-exchange instruction. */
|
||||
@ -4469,9 +4486,9 @@ displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc,
|
||||
|
||||
/* This function is used to concisely determine if an instruction INSN
|
||||
references PC. Register fields of interest in INSN should have the
|
||||
corresponding fields of BITMASK set to 0b1111. The function returns return 1
|
||||
if any of these fields in INSN reference the PC (also 0b1111, r15), else it
|
||||
returns 0. */
|
||||
corresponding fields of BITMASK set to 0b1111. The function
|
||||
returns return 1 if any of these fields in INSN reference the PC
|
||||
(also 0b1111, r15), else it returns 0. */
|
||||
|
||||
static int
|
||||
insn_references_pc (uint32_t insn, uint32_t bitmask)
|
||||
@ -4564,7 +4581,8 @@ copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
|
||||
/* Preload instructions with register offset. */
|
||||
|
||||
static int
|
||||
copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
|
||||
copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn,
|
||||
struct regcache *regs,
|
||||
struct displaced_step_closure *dsc)
|
||||
{
|
||||
unsigned int rn = bits (insn, 16, 19);
|
||||
@ -4741,7 +4759,8 @@ copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn,
|
||||
|
||||
if (debug_displaced)
|
||||
fprintf_unfiltered (gdb_stdlog, "displaced: copying %s register insn "
|
||||
"%.8lx\n", (link) ? "blx" : "bx", (unsigned long) insn);
|
||||
"%.8lx\n", (link) ? "blx" : "bx",
|
||||
(unsigned long) insn);
|
||||
|
||||
/* Implement {BX,BLX}<cond> <reg>" as:
|
||||
|
||||
@ -4764,7 +4783,7 @@ copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn,
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
|
||||
/* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
|
||||
|
||||
static void
|
||||
cleanup_alu_imm (struct gdbarch *gdbarch,
|
||||
@ -4912,7 +4931,8 @@ cleanup_alu_shifted_reg (struct gdbarch *gdbarch,
|
||||
|
||||
static int
|
||||
copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn,
|
||||
struct regcache *regs, struct displaced_step_closure *dsc)
|
||||
struct regcache *regs,
|
||||
struct displaced_step_closure *dsc)
|
||||
{
|
||||
unsigned int rn = bits (insn, 16, 19);
|
||||
unsigned int rm = bits (insn, 0, 3);
|
||||
@ -5426,13 +5446,15 @@ copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
|
||||
int rn = bits (insn, 16, 19);
|
||||
CORE_ADDR from = dsc->insn_addr;
|
||||
|
||||
/* Block transfers which don't mention PC can be run directly out-of-line. */
|
||||
/* Block transfers which don't mention PC can be run directly
|
||||
out-of-line. */
|
||||
if (rn != 15 && (insn & 0x8000) == 0)
|
||||
return copy_unmodified (gdbarch, insn, "ldm/stm", dsc);
|
||||
|
||||
if (rn == 15)
|
||||
{
|
||||
warning (_("displaced: Unpredictable LDM or STM with base register r15"));
|
||||
warning (_("displaced: Unpredictable LDM or STM with "
|
||||
"base register r15"));
|
||||
return copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc);
|
||||
}
|
||||
|
||||
@ -5578,7 +5600,8 @@ copy_undef (struct gdbarch *gdbarch, uint32_t insn,
|
||||
struct displaced_step_closure *dsc)
|
||||
{
|
||||
if (debug_displaced)
|
||||
fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn %.8lx\n",
|
||||
fprintf_unfiltered (gdb_stdlog,
|
||||
"displaced: copying undefined insn %.8lx\n",
|
||||
(unsigned long) insn);
|
||||
|
||||
dsc->modinsn[0] = insn;
|
||||
@ -5665,7 +5688,8 @@ decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
|
||||
|
||||
static int
|
||||
decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
|
||||
struct regcache *regs, struct displaced_step_closure *dsc)
|
||||
struct regcache *regs,
|
||||
struct displaced_step_closure *dsc)
|
||||
{
|
||||
if (bit (insn, 27) == 0)
|
||||
return decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
|
||||
@ -5749,7 +5773,8 @@ decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
|
||||
|
||||
static int
|
||||
decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
|
||||
struct regcache *regs, struct displaced_step_closure *dsc)
|
||||
struct regcache *regs,
|
||||
struct displaced_step_closure *dsc)
|
||||
{
|
||||
unsigned int op2 = bits (insn, 4, 6);
|
||||
unsigned int op = bits (insn, 21, 22);
|
||||
@ -5777,7 +5802,8 @@ decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
|
||||
|
||||
case 0x3:
|
||||
if (op == 0x1)
|
||||
return copy_bx_blx_reg (gdbarch, insn, regs, dsc); /* blx register. */
|
||||
return copy_bx_blx_reg (gdbarch, insn,
|
||||
regs, dsc); /* blx register. */
|
||||
else
|
||||
return copy_undef (gdbarch, insn, dsc);
|
||||
|
||||
@ -5947,7 +5973,8 @@ decode_b_bl_ldmstm (struct gdbarch *gdbarch, int32_t insn,
|
||||
|
||||
static int
|
||||
decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
|
||||
struct regcache *regs, struct displaced_step_closure *dsc)
|
||||
struct regcache *regs,
|
||||
struct displaced_step_closure *dsc)
|
||||
{
|
||||
unsigned int opcode = bits (insn, 20, 24);
|
||||
|
||||
@ -6023,7 +6050,8 @@ decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
|
||||
|
||||
void
|
||||
arm_process_displaced_insn (struct gdbarch *gdbarch, uint32_t insn,
|
||||
CORE_ADDR from, CORE_ADDR to, struct regcache *regs,
|
||||
CORE_ADDR from, CORE_ADDR to,
|
||||
struct regcache *regs,
|
||||
struct displaced_step_closure *dsc)
|
||||
{
|
||||
int err = 0;
|
||||
@ -6205,7 +6233,7 @@ gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
|
||||
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
|
||||
C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
|
||||
|
||||
Even this may only true if the condition predicate is true. The
|
||||
Even this may only true if the condition predicate is true. The
|
||||
following use a condition predicate of ALWAYS so it is always TRUE.
|
||||
|
||||
There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
|
||||
@ -6322,9 +6350,9 @@ arm_extract_return_value (struct type *type, struct regcache *regs,
|
||||
break;
|
||||
|
||||
default:
|
||||
internal_error
|
||||
(__FILE__, __LINE__,
|
||||
_("arm_extract_return_value: Floating point model not supported"));
|
||||
internal_error (__FILE__, __LINE__,
|
||||
_("arm_extract_return_value: "
|
||||
"Floating point model not supported"));
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -6449,7 +6477,8 @@ arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
|
||||
for (i = 0; i < TYPE_NFIELDS (type); i++)
|
||||
{
|
||||
enum type_code field_type_code;
|
||||
field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
|
||||
field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type,
|
||||
i)));
|
||||
|
||||
/* Is it a floating point type field? */
|
||||
if (field_type_code == TYPE_CODE_FLT)
|
||||
@ -6841,8 +6870,9 @@ arm_show_fallback_mode (struct ui_file *file, int from_tty,
|
||||
{
|
||||
struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
|
||||
|
||||
fprintf_filtered (file, _("\
|
||||
The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
|
||||
fprintf_filtered (file,
|
||||
_("The current execution mode assumed "
|
||||
"(when symbols are unavailable) is \"%s\".\n"),
|
||||
arm_fallback_mode_string);
|
||||
}
|
||||
|
||||
@ -6852,8 +6882,9 @@ arm_show_force_mode (struct ui_file *file, int from_tty,
|
||||
{
|
||||
struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
|
||||
|
||||
fprintf_filtered (file, _("\
|
||||
The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
|
||||
fprintf_filtered (file,
|
||||
_("The current execution mode assumed "
|
||||
"(even when symbols are available) is \"%s\".\n"),
|
||||
arm_force_mode_string);
|
||||
}
|
||||
|
||||
@ -7333,7 +7364,8 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
|
||||
not. */
|
||||
attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
|
||||
Tag_CPU_arch);
|
||||
attr_profile = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
|
||||
attr_profile = bfd_elf_get_obj_attr_int (info.abfd,
|
||||
OBJ_ATTR_PROC,
|
||||
Tag_CPU_arch_profile);
|
||||
/* GCC specifies the profile for v6-M; RealView only
|
||||
specifies the profile for architectures starting with
|
||||
@ -7875,7 +7907,8 @@ _initialize_arm_tdep (void)
|
||||
_("Show the disassembly style."),
|
||||
helptext,
|
||||
set_disassembly_style_sfunc,
|
||||
NULL, /* FIXME: i18n: The disassembly style is \"%s\". */
|
||||
NULL, /* FIXME: i18n: The disassembly style is
|
||||
\"%s\". */
|
||||
&setarmcmdlist, &showarmcmdlist);
|
||||
|
||||
add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
|
||||
@ -7883,7 +7916,8 @@ _initialize_arm_tdep (void)
|
||||
_("Show usage of ARM 32-bit mode."),
|
||||
_("When off, a 26-bit PC will be used."),
|
||||
NULL,
|
||||
NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
|
||||
NULL, /* FIXME: i18n: Usage of ARM 32-bit
|
||||
mode is %s. */
|
||||
&setarmcmdlist, &showarmcmdlist);
|
||||
|
||||
/* Add a command to allow the user to force the FPU model. */
|
||||
|
||||
Reference in New Issue
Block a user