espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-24 20:28:28 +08:00
Code Issues Packages Projects Releases Wiki Activity

* config/tc-arm.c (md_assemble): Allow barrier instructions on

Browse Source 
ARMv6-M cores.

	* gas/arm/archv6m.s: Add dmb, dsb, and isb.
	* gas/arm/archv6m.d: Likewise.
This commit is contained in:
Mark Mitchell
2009-03-02 00:29:23 +00:00
parent c493b4aa97
commit 04e2c417f9
5 changed files with 21 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2009-03-01 Mark Mitchell <mark@codesourcery.com>
* config/tc-arm.c (md_assemble): Allow barrier instructions on
ARMv6-M cores.
2009-03-01 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> 2009-03-01 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
* configure: Regenerate. * configure: Regenerate.

6
gas/config/tc-arm.c
View File

@ -14747,7 +14747,8 @@ md_assemble (char *str)
/* Implicit require narrow instructions on Thumb-1. This avoids /* Implicit require narrow instructions on Thumb-1. This avoids
relaxation accidentally introducing Thumb-2 instructions. */ relaxation accidentally introducing Thumb-2 instructions. */
if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
&& !ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)) && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
|| ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
inst.size_req = 2; inst.size_req = 2;
} }
@ -14805,7 +14806,8 @@ md_assemble (char *str)
This is overly pessimistic for relaxable instructions. */ This is overly pessimistic for relaxable instructions. */
if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
|| inst.relax) || inst.relax)
&& !ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)) && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
|| ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
arm_ext_v6t2); arm_ext_v6t2);
} }

5
gas/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2009-03-01 Mark Mitchell <mark@codesourcery.com>
* gas/arm/archv6m.s: Add dmb, dsb, and isb.
* gas/arm/archv6m.d: Likewise.
2009-02-26 Peter Bergner <bergner@vnet.ibm.com> 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
* gas/ppc/e500mc.d ("wait", "waitsrv", "waitimpl"): Add tests. * gas/ppc/e500mc.d ("wait", "waitsrv", "waitimpl"): Add tests.

3
gas/testsuite/gas/arm/archv6m.d
View File

@ -13,3 +13,6 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> bf40 sev 0[0-9a-f]+ <[^>]+> bf40 sev
0[0-9a-f]+ <[^>]+> 4408 add r0, r1 0[0-9a-f]+ <[^>]+> 4408 add r0, r1
0[0-9a-f]+ <[^>]+> 46c0 nop.* 0[0-9a-f]+ <[^>]+> 46c0 nop.*
0[0-9a-f]+ <[^>]+> f3bf 8f5f dmb sy
0[0-9a-f]+ <[^>]+> f3bf 8f4f dsb sy
0[0-9a-f]+ <[^>]+> f3bf 8f6f isb sy

4
gas/testsuite/gas/arm/archv6m.s
View File

@ -14,3 +14,7 @@ foo:
sev sev
add r0, r0, r1 add r0, r0, r1
nop nop
dmb
dsb
isb