mirror of
https://github.com/espressif/binutils-gdb.git
synced 2025-06-19 09:14:14 +08:00
RISC-V: Added half-precision floating-point v1.0 instructions.
bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Added implicit f and zicsr for zfh. (riscv_supported_std_z_ext): Added default v1.0 version for zfh. (riscv_multi_subset_supports): Handle INSN_CLASS_ZFH, INSN_CLASS_D_AND_ZFH and INSN_CLASS_Q_AND_ZFH. gas/ * config/tc-riscv.c (FLT_CHARS): Added "hH". (macro): Expand Pseudo M_FLH and M_FSH. (riscv_pseudo_table): Added .float16 directive. * testsuite/gas/riscv/float16-be.d: New testcase for .float16. * testsuite/gas/riscv/float16-le.d: Likewise. * testsuite/gas/riscv/float16.s: Likewise. * testsuite/gas/riscv/fp-zfh-insns.d: New testcase for zfh. * testsuite/gas/riscv/fp-zfh-insns.s: Likewise. include/ * opcode/riscv-opc.h: Added MASK and MATCH encodings for zfh. * opcode/riscv.h: Added INSN_CLASS and pseudo macros for zfh. opcodes/ * riscv-opc.c (riscv_opcodes): Added zfh instructions.
This commit is contained in:
Nelson Chu
@ -1100,6 +1100,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
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{"zvl64b", "zvl32b", check_implicit_always},
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{"d", "f", check_implicit_always},
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{"f", "zicsr", check_implicit_always},
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{"zfh", "f", check_implicit_always},
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{"zfh", "zicsr", check_implicit_always},
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{"zqinx", "zdinx", check_implicit_always},
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{"zdinx", "zfinx", check_implicit_always},
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{"zk", "zkn", check_implicit_always},
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@ -1180,6 +1182,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
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{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
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{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
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{"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zdinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zqinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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@ -2358,6 +2361,14 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
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case INSN_CLASS_Q_OR_ZQINX:
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return (riscv_subset_supports (rps, "q")
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|| riscv_subset_supports (rps, "zqinx"));
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case INSN_CLASS_ZFH:
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return riscv_subset_supports (rps, "zfh");
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case INSN_CLASS_D_AND_ZFH:
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return (riscv_subset_supports (rps, "d")
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&& riscv_subset_supports (rps, "zfh") );
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case INSN_CLASS_Q_AND_ZFH:
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return (riscv_subset_supports (rps, "q")
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&& riscv_subset_supports (rps, "zfh"));
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case INSN_CLASS_ZBA:
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return riscv_subset_supports (rps, "zba");
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case INSN_CLASS_ZBB:
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@ -389,7 +389,7 @@ const char EXP_CHARS[] = "eE";
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/* Chars that mean this number is a floating point constant.
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As in 0f12.456 or 0d1.2345e12. */
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const char FLT_CHARS[] = "rRsSfFdDxXpP";
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const char FLT_CHARS[] = "rRsSfFdDxXpPhH";
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/* Indicate we are already assemble any instructions or not. */
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static bool start_assemble = false;
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@ -1908,6 +1908,15 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
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vector_macro (ip);
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break;
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case M_FLH:
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pcrel_load (rd, rs1, imm_expr, "flh",
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BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
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break;
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case M_FSH:
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pcrel_store (rs2, rs1, imm_expr, "fsh",
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BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
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break;
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default:
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as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name);
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break;
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@ -4569,6 +4578,7 @@ static const pseudo_typeS riscv_pseudo_table[] =
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{"insn", s_riscv_insn, 0},
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{"attribute", s_riscv_attribute, 0},
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{"variant_cc", s_variant_cc, 0},
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{"float16", float_cons, 'h'},
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{ NULL, NULL, 0 },
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};
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10
gas/testsuite/gas/riscv/float16-be.d
Normal file
10
gas/testsuite/gas/riscv/float16-be.d
Normal file
@ -0,0 +1,10 @@
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# source: float16.s
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# objdump: -sj .data
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# as: -mbig-endian
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.*:[ ]+file format .*bigriscv
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Contents of section \.data:
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0000 4a002fdf 1c197bff 000103ff 04003c00.*
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0010 3c017fff 7c00fc00 00008000 bc00bbe7.*
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0020 fbff4200 4a00603e 7e007c01.*
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10
gas/testsuite/gas/riscv/float16-le.d
Normal file
10
gas/testsuite/gas/riscv/float16-le.d
Normal file
@ -0,0 +1,10 @@
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# source: float16.s
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# objdump: -sj .data
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# as: -mlittle-endian
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.*:[ ]+file format .*littleriscv
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Contents of section \.data:
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0000 004adf2f 191cff7b 0100ff03 0004003c.*
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0010 013cff7f 007c00fc 00000080 00bce7bb.*
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0020 fffb0042 004a3e60 007e017c.*
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21
gas/testsuite/gas/riscv/float16.s
Normal file
21
gas/testsuite/gas/riscv/float16.s
Normal file
@ -0,0 +1,21 @@
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.data
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.float16 12.0
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.float16 0.123
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.float16 0.004
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.float16 65504
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.float16 5.9605e-8
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.float16 6.0976e-5
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.float16 6.1035e-5
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.float16 1
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.float16 1.001
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.float16 NaN
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.float16 +Inf
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.float16 -Inf
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.float16 +0
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.float16 -0
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.float16 -1
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.float16 -0.98765
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.float16 -65504
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.float16 3.0, 12.0, 543.123
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.float16 0h:7e00 # qNaNh
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.float16 0h:7c01 # sNaNh
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71
gas/testsuite/gas/riscv/fp-zfh-insns.d
Normal file
71
gas/testsuite/gas/riscv/fp-zfh-insns.d
Normal file
@ -0,0 +1,71 @@
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#as: -march=rv64ifdq_zfh
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#source: fp-zfh-insns.s
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#objdump: -dr
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.*:[ ]+file format .*
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Disassembly of section .text:
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0+000 <.text>:
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[ ]+[0-9a-f]+:[ ]+00059507[ ]+flh[ ]+fa0,0\(a1\)
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[ ]+[0-9a-f]+:[ ]+00a59027[ ]+fsh[ ]+fa0,0\(a1\)
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[ ]+[0-9a-f]+:[ ]+24b58553[ ]+fmv.h[ ]+fa0,fa1
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[ ]+[0-9a-f]+:[ ]+24b59553[ ]+fneg.h[ ]+fa0,fa1
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[ ]+[0-9a-f]+:[ ]+24b5a553[ ]+fabs.h[ ]+fa0,fa1
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[ ]+[0-9a-f]+:[ ]+24c58553[ ]+fsgnj.h[ ]+fa0,fa1,fa2
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[ ]+[0-9a-f]+:[ ]+24c59553[ ]+fsgnjn.h[ ]+fa0,fa1,fa2
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[ ]+[0-9a-f]+:[ ]+24c5a553[ ]+fsgnjx.h[ ]+fa0,fa1,fa2
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[ ]+[0-9a-f]+:[ ]+04c5f553[ ]+fadd.h[ ]+fa0,fa1,fa2
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[ ]+[0-9a-f]+:[ ]+04c58553[ ]+fadd.h[ ]+fa0,fa1,fa2,rne
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[ ]+[0-9a-f]+:[ ]+0cc5f553[ ]+fsub.h[ ]+fa0,fa1,fa2
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[ ]+[0-9a-f]+:[ ]+0cc58553[ ]+fsub.h[ ]+fa0,fa1,fa2,rne
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[ ]+[0-9a-f]+:[ ]+14c5f553[ ]+fmul.h[ ]+fa0,fa1,fa2
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[ ]+[0-9a-f]+:[ ]+14c58553[ ]+fmul.h[ ]+fa0,fa1,fa2,rne
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[ ]+[0-9a-f]+:[ ]+1cc5f553[ ]+fdiv.h[ ]+fa0,fa1,fa2
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[ ]+[0-9a-f]+:[ ]+1cc58553[ ]+fdiv.h[ ]+fa0,fa1,fa2,rne
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[ ]+[0-9a-f]+:[ ]+5c05f553[ ]+fsqrt.h[ ]+fa0,fa1
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[ ]+[0-9a-f]+:[ ]+5c058553[ ]+fsqrt.h[ ]+fa0,fa1,rne
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[ ]+[0-9a-f]+:[ ]+2cc58553[ ]+fmin.h[ ]+fa0,fa1,fa2
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[ ]+[0-9a-f]+:[ ]+2cc59553[ ]+fmax.h[ ]+fa0,fa1,fa2
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[ ]+[0-9a-f]+:[ ]+6cc5f543[ ]+fmadd.h[ ]+fa0,fa1,fa2,fa3
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[ ]+[0-9a-f]+:[ ]+6cc58543[ ]+fmadd.h[ ]+fa0,fa1,fa2,fa3,rne
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[ ]+[0-9a-f]+:[ ]+6cc5f54f[ ]+fnmadd.h[ ]+fa0,fa1,fa2,fa3
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[ ]+[0-9a-f]+:[ ]+6cc5854f[ ]+fnmadd.h[ ]+fa0,fa1,fa2,fa3,rne
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[ ]+[0-9a-f]+:[ ]+6cc5f547[ ]+fmsub.h[ ]+fa0,fa1,fa2,fa3
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[ ]+[0-9a-f]+:[ ]+6cc58547[ ]+fmsub.h[ ]+fa0,fa1,fa2,fa3,rne
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[ ]+[0-9a-f]+:[ ]+6cc5f54b[ ]+fnmsub.h[ ]+fa0,fa1,fa2,fa3
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[ ]+[0-9a-f]+:[ ]+6cc5854b[ ]+fnmsub.h[ ]+fa0,fa1,fa2,fa3,rne
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[ ]+[0-9a-f]+:[ ]+c405f553[ ]+fcvt.w.h[ ]+a0,fa1
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[ ]+[0-9a-f]+:[ ]+c4058553[ ]+fcvt.w.h[ ]+a0,fa1,rne
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[ ]+[0-9a-f]+:[ ]+c415f553[ ]+fcvt.wu.h[ ]+a0,fa1
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[ ]+[0-9a-f]+:[ ]+c4158553[ ]+fcvt.wu.h[ ]+a0,fa1,rne
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[ ]+[0-9a-f]+:[ ]+d405f553[ ]+fcvt.h.w[ ]+fa0,a1
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[ ]+[0-9a-f]+:[ ]+d4058553[ ]+fcvt.h.w[ ]+fa0,a1,rne
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[ ]+[0-9a-f]+:[ ]+d415f553[ ]+fcvt.h.wu[ ]+fa0,a1
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[ ]+[0-9a-f]+:[ ]+d4158553[ ]+fcvt.h.wu[ ]+fa0,a1,rne
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[ ]+[0-9a-f]+:[ ]+c425f553[ ]+fcvt.l.h[ ]+a0,fa1
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[ ]+[0-9a-f]+:[ ]+c4258553[ ]+fcvt.l.h[ ]+a0,fa1,rne
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[ ]+[0-9a-f]+:[ ]+c435f553[ ]+fcvt.lu.h[ ]+a0,fa1
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[ ]+[0-9a-f]+:[ ]+c4358553[ ]+fcvt.lu.h[ ]+a0,fa1,rne
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[ ]+[0-9a-f]+:[ ]+d425f553[ ]+fcvt.h.l[ ]+fa0,a1
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[ ]+[0-9a-f]+:[ ]+d4258553[ ]+fcvt.h.l[ ]+fa0,a1,rne
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[ ]+[0-9a-f]+:[ ]+d435f553[ ]+fcvt.h.lu[ ]+fa0,a1
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[ ]+[0-9a-f]+:[ ]+d4358553[ ]+fcvt.h.lu[ ]+fa0,a1,rne
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[ ]+[0-9a-f]+:[ ]+e4058553[ ]+fmv.x.h[ ]+a0,fa1
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[ ]+[0-9a-f]+:[ ]+f4058553[ ]+fmv.h.x[ ]+fa0,a1
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[ ]+[0-9a-f]+:[ ]+40258553[ ]+fcvt.s.h[ ]+fa0,fa1
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[ ]+[0-9a-f]+:[ ]+42258553[ ]+fcvt.d.h[ ]+fa0,fa1
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||||
[ ]+[0-9a-f]+:[ ]+46258553[ ]+fcvt.q.h[ ]+fa0,fa1
|
||||
[ ]+[0-9a-f]+:[ ]+4405f553[ ]+fcvt.h.s[ ]+fa0,fa1
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[ ]+[0-9a-f]+:[ ]+44058553[ ]+fcvt.h.s[ ]+fa0,fa1,rne
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||||
[ ]+[0-9a-f]+:[ ]+4415f553[ ]+fcvt.h.d[ ]+fa0,fa1
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[ ]+[0-9a-f]+:[ ]+44158553[ ]+fcvt.h.d[ ]+fa0,fa1,rne
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||||
[ ]+[0-9a-f]+:[ ]+4435f553[ ]+fcvt.h.q[ ]+fa0,fa1
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||||
[ ]+[0-9a-f]+:[ ]+44358553[ ]+fcvt.h.q[ ]+fa0,fa1,rne
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||||
[ ]+[0-9a-f]+:[ ]+e4059553[ ]+fclass.h[ ]+a0,fa1
|
||||
[ ]+[0-9a-f]+:[ ]+a4c5a553[ ]+feq.h[ ]+a0,fa1,fa2
|
||||
[ ]+[0-9a-f]+:[ ]+a4c59553[ ]+flt.h[ ]+a0,fa1,fa2
|
||||
[ ]+[0-9a-f]+:[ ]+a4c58553[ ]+fle.h[ ]+a0,fa1,fa2
|
||||
[ ]+[0-9a-f]+:[ ]+a4c59553[ ]+flt.h[ ]+a0,fa1,fa2
|
||||
[ ]+[0-9a-f]+:[ ]+a4c58553[ ]+fle.h[ ]+a0,fa1,fa2
|
||||
68
gas/testsuite/gas/riscv/fp-zfh-insns.s
Normal file
68
gas/testsuite/gas/riscv/fp-zfh-insns.s
Normal file
@ -0,0 +1,68 @@
|
||||
flh fa0, 0(a1)
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fsh fa0, 0(a1)
|
||||
|
||||
fmv.h fa0, fa1
|
||||
fneg.h fa0, fa1
|
||||
fabs.h fa0, fa1
|
||||
fsgnj.h fa0, fa1, fa2
|
||||
fsgnjn.h fa0, fa1, fa2
|
||||
fsgnjx.h fa0, fa1, fa2
|
||||
|
||||
fadd.h fa0, fa1, fa2
|
||||
fadd.h fa0, fa1, fa2, rne
|
||||
fsub.h fa0, fa1, fa2
|
||||
fsub.h fa0, fa1, fa2, rne
|
||||
fmul.h fa0, fa1, fa2
|
||||
fmul.h fa0, fa1, fa2, rne
|
||||
fdiv.h fa0, fa1, fa2
|
||||
fdiv.h fa0, fa1, fa2, rne
|
||||
fsqrt.h fa0, fa1
|
||||
fsqrt.h fa0, fa1, rne
|
||||
fmin.h fa0, fa1, fa2
|
||||
fmax.h fa0, fa1, fa2
|
||||
|
||||
fmadd.h fa0, fa1, fa2, fa3
|
||||
fmadd.h fa0, fa1, fa2, fa3, rne
|
||||
fnmadd.h fa0, fa1, fa2, fa3
|
||||
fnmadd.h fa0, fa1, fa2, fa3, rne
|
||||
fmsub.h fa0, fa1, fa2, fa3
|
||||
fmsub.h fa0, fa1, fa2, fa3, rne
|
||||
fnmsub.h fa0, fa1, fa2, fa3
|
||||
fnmsub.h fa0, fa1, fa2, fa3, rne
|
||||
|
||||
fcvt.w.h a0, fa1
|
||||
fcvt.w.h a0, fa1, rne
|
||||
fcvt.wu.h a0, fa1
|
||||
fcvt.wu.h a0, fa1, rne
|
||||
fcvt.h.w fa0, a1
|
||||
fcvt.h.w fa0, a1, rne
|
||||
fcvt.h.wu fa0, a1
|
||||
fcvt.h.wu fa0, a1, rne
|
||||
fcvt.l.h a0, fa1
|
||||
fcvt.l.h a0, fa1, rne
|
||||
fcvt.lu.h a0, fa1
|
||||
fcvt.lu.h a0, fa1, rne
|
||||
fcvt.h.l fa0, a1
|
||||
fcvt.h.l fa0, a1, rne
|
||||
fcvt.h.lu fa0, a1
|
||||
fcvt.h.lu fa0, a1, rne
|
||||
|
||||
fmv.x.h a0, fa1
|
||||
fmv.h.x fa0, a1
|
||||
|
||||
fcvt.s.h fa0, fa1
|
||||
fcvt.d.h fa0, fa1
|
||||
fcvt.q.h fa0, fa1
|
||||
fcvt.h.s fa0, fa1
|
||||
fcvt.h.s fa0, fa1, rne
|
||||
fcvt.h.d fa0, fa1
|
||||
fcvt.h.d fa0, fa1, rne
|
||||
fcvt.h.q fa0, fa1
|
||||
fcvt.h.q fa0, fa1, rne
|
||||
fclass.h a0, fa1
|
||||
|
||||
feq.h a0, fa1, fa2
|
||||
flt.h a0, fa1, fa2
|
||||
fle.h a0, fa1, fa2
|
||||
fgt.h a0, fa2, fa1
|
||||
fge.h a0, fa2, fa1
|
||||
@ -705,6 +705,78 @@
|
||||
#define MASK_AES64DSM 0xfe00707f
|
||||
#define MATCH_AES64DS 0x3a000033
|
||||
#define MASK_AES64DS 0xfe00707f
|
||||
#define MATCH_FADD_H 0x4000053
|
||||
#define MASK_FADD_H 0xfe00007f
|
||||
#define MATCH_FSUB_H 0xc000053
|
||||
#define MASK_FSUB_H 0xfe00007f
|
||||
#define MATCH_FMUL_H 0x14000053
|
||||
#define MASK_FMUL_H 0xfe00007f
|
||||
#define MATCH_FDIV_H 0x1c000053
|
||||
#define MASK_FDIV_H 0xfe00007f
|
||||
#define MATCH_FSGNJ_H 0x24000053
|
||||
#define MASK_FSGNJ_H 0xfe00707f
|
||||
#define MATCH_FSGNJN_H 0x24001053
|
||||
#define MASK_FSGNJN_H 0xfe00707f
|
||||
#define MATCH_FSGNJX_H 0x24002053
|
||||
#define MASK_FSGNJX_H 0xfe00707f
|
||||
#define MATCH_FMIN_H 0x2c000053
|
||||
#define MASK_FMIN_H 0xfe00707f
|
||||
#define MATCH_FMAX_H 0x2c001053
|
||||
#define MASK_FMAX_H 0xfe00707f
|
||||
#define MATCH_FCVT_H_S 0x44000053
|
||||
#define MASK_FCVT_H_S 0xfff0007f
|
||||
#define MATCH_FCVT_S_H 0x40200053
|
||||
#define MASK_FCVT_S_H 0xfff0007f
|
||||
#define MATCH_FSQRT_H 0x5c000053
|
||||
#define MASK_FSQRT_H 0xfff0007f
|
||||
#define MATCH_FLE_H 0xa4000053
|
||||
#define MASK_FLE_H 0xfe00707f
|
||||
#define MATCH_FLT_H 0xa4001053
|
||||
#define MASK_FLT_H 0xfe00707f
|
||||
#define MATCH_FEQ_H 0xa4002053
|
||||
#define MASK_FEQ_H 0xfe00707f
|
||||
#define MATCH_FCVT_W_H 0xc4000053
|
||||
#define MASK_FCVT_W_H 0xfff0007f
|
||||
#define MATCH_FCVT_WU_H 0xc4100053
|
||||
#define MASK_FCVT_WU_H 0xfff0007f
|
||||
#define MATCH_FMV_X_H 0xe4000053
|
||||
#define MASK_FMV_X_H 0xfff0707f
|
||||
#define MATCH_FCLASS_H 0xe4001053
|
||||
#define MASK_FCLASS_H 0xfff0707f
|
||||
#define MATCH_FCVT_H_W 0xd4000053
|
||||
#define MASK_FCVT_H_W 0xfff0007f
|
||||
#define MATCH_FCVT_H_WU 0xd4100053
|
||||
#define MASK_FCVT_H_WU 0xfff0007f
|
||||
#define MATCH_FMV_H_X 0xf4000053
|
||||
#define MASK_FMV_H_X 0xfff0707f
|
||||
#define MATCH_FLH 0x1007
|
||||
#define MASK_FLH 0x707f
|
||||
#define MATCH_FSH 0x1027
|
||||
#define MASK_FSH 0x707f
|
||||
#define MATCH_FMADD_H 0x4000043
|
||||
#define MASK_FMADD_H 0x600007f
|
||||
#define MATCH_FMSUB_H 0x4000047
|
||||
#define MASK_FMSUB_H 0x600007f
|
||||
#define MATCH_FNMSUB_H 0x400004b
|
||||
#define MASK_FNMSUB_H 0x600007f
|
||||
#define MATCH_FNMADD_H 0x400004f
|
||||
#define MASK_FNMADD_H 0x600007f
|
||||
#define MATCH_FCVT_H_D 0x44100053
|
||||
#define MASK_FCVT_H_D 0xfff0007f
|
||||
#define MATCH_FCVT_D_H 0x42200053
|
||||
#define MASK_FCVT_D_H 0xfff0007f
|
||||
#define MATCH_FCVT_H_Q 0x44300053
|
||||
#define MASK_FCVT_H_Q 0xfff0007f
|
||||
#define MATCH_FCVT_Q_H 0x46200053
|
||||
#define MASK_FCVT_Q_H 0xfff0007f
|
||||
#define MATCH_FCVT_L_H 0xc4200053
|
||||
#define MASK_FCVT_L_H 0xfff0007f
|
||||
#define MATCH_FCVT_LU_H 0xc4300053
|
||||
#define MASK_FCVT_LU_H 0xfff0007f
|
||||
#define MATCH_FCVT_H_L 0xd4200053
|
||||
#define MASK_FCVT_H_L 0xfff0007f
|
||||
#define MATCH_FCVT_H_LU 0xd4300053
|
||||
#define MASK_FCVT_H_LU 0xfff0007f
|
||||
#define MATCH_VSETVL 0x80007057
|
||||
#define MASK_VSETVL 0xfe00707f
|
||||
#define MATCH_VSETIVLI 0xc0007057
|
||||
|
||||
@ -370,6 +370,9 @@ enum riscv_insn_class
|
||||
INSN_CLASS_F_OR_ZFINX,
|
||||
INSN_CLASS_D_OR_ZDINX,
|
||||
INSN_CLASS_Q_OR_ZQINX,
|
||||
INSN_CLASS_ZFH,
|
||||
INSN_CLASS_D_AND_ZFH,
|
||||
INSN_CLASS_Q_AND_ZFH,
|
||||
INSN_CLASS_ZBA,
|
||||
INSN_CLASS_ZBB,
|
||||
INSN_CLASS_ZBC,
|
||||
@ -498,6 +501,8 @@ enum
|
||||
M_SEXTH,
|
||||
M_VMSGE,
|
||||
M_VMSGEU,
|
||||
M_FLH,
|
||||
M_FSH,
|
||||
M_NUM_MACROS
|
||||
};
|
||||
|
||||
|
||||
@ -572,6 +572,71 @@ const struct riscv_opcode riscv_opcodes[] =
|
||||
{"remw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 },
|
||||
{"remuw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
|
||||
|
||||
/* Half-precision floating-point instruction subset. */
|
||||
{"flh", 0, INSN_CLASS_ZFH, "D,o(s)", MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
|
||||
{"flh", 0, INSN_CLASS_ZFH, "D,A,s", 0, (int) M_FLH, match_never, INSN_MACRO },
|
||||
{"fsh", 0, INSN_CLASS_ZFH, "T,q(s)", MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE },
|
||||
{"fsh", 0, INSN_CLASS_ZFH, "T,A,s", 0, (int) M_FSH, match_never, INSN_MACRO },
|
||||
{"fmv.h", 0, INSN_CLASS_ZFH, "D,U", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS },
|
||||
{"fneg.h", 0, INSN_CLASS_ZFH, "D,U", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_rs1_eq_rs2, INSN_ALIAS },
|
||||
{"fabs.h", 0, INSN_CLASS_ZFH, "D,U", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_rs1_eq_rs2, INSN_ALIAS },
|
||||
{"fsgnj.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 },
|
||||
{"fsgnjn.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 },
|
||||
{"fsgnjx.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 },
|
||||
{"fadd.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FADD_H|MASK_RM, MASK_FADD_H|MASK_RM, match_opcode, 0 },
|
||||
{"fadd.h", 0, INSN_CLASS_ZFH, "D,S,T,m", MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 },
|
||||
{"fsub.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FSUB_H|MASK_RM, MASK_FSUB_H|MASK_RM, match_opcode, 0 },
|
||||
{"fsub.h", 0, INSN_CLASS_ZFH, "D,S,T,m", MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 },
|
||||
{"fmul.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FMUL_H|MASK_RM, MASK_FMUL_H|MASK_RM, match_opcode, 0 },
|
||||
{"fmul.h", 0, INSN_CLASS_ZFH, "D,S,T,m", MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 },
|
||||
{"fdiv.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FDIV_H|MASK_RM, MASK_FDIV_H|MASK_RM, match_opcode, 0 },
|
||||
{"fdiv.h", 0, INSN_CLASS_ZFH, "D,S,T,m", MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 },
|
||||
{"fsqrt.h", 0, INSN_CLASS_ZFH, "D,S", MATCH_FSQRT_H|MASK_RM, MASK_FSQRT_H|MASK_RM, match_opcode, 0 },
|
||||
{"fsqrt.h", 0, INSN_CLASS_ZFH, "D,S,m", MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 },
|
||||
{"fmin.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 },
|
||||
{"fmax.h", 0, INSN_CLASS_ZFH, "D,S,T", MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 },
|
||||
{"fmadd.h", 0, INSN_CLASS_ZFH, "D,S,T,R", MATCH_FMADD_H|MASK_RM, MASK_FMADD_H|MASK_RM, match_opcode, 0 },
|
||||
{"fmadd.h", 0, INSN_CLASS_ZFH, "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 },
|
||||
{"fnmadd.h", 0, INSN_CLASS_ZFH, "D,S,T,R", MATCH_FNMADD_H|MASK_RM, MASK_FNMADD_H|MASK_RM, match_opcode, 0 },
|
||||
{"fnmadd.h", 0, INSN_CLASS_ZFH, "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 },
|
||||
{"fmsub.h", 0, INSN_CLASS_ZFH, "D,S,T,R", MATCH_FMSUB_H|MASK_RM, MASK_FMSUB_H|MASK_RM, match_opcode, 0 },
|
||||
{"fmsub.h", 0, INSN_CLASS_ZFH, "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 },
|
||||
{"fnmsub.h", 0, INSN_CLASS_ZFH, "D,S,T,R", MATCH_FNMSUB_H|MASK_RM, MASK_FNMSUB_H|MASK_RM, match_opcode, 0 },
|
||||
{"fnmsub.h", 0, INSN_CLASS_ZFH, "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 },
|
||||
{"fcvt.w.h", 0, INSN_CLASS_ZFH, "d,S", MATCH_FCVT_W_H|MASK_RM, MASK_FCVT_W_H|MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.w.h", 0, INSN_CLASS_ZFH, "d,S,m", MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 },
|
||||
{"fcvt.wu.h", 0, INSN_CLASS_ZFH, "d,S", MATCH_FCVT_WU_H|MASK_RM, MASK_FCVT_WU_H|MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.wu.h", 0, INSN_CLASS_ZFH, "d,S,m", MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 },
|
||||
{"fcvt.h.w", 0, INSN_CLASS_ZFH, "D,s", MATCH_FCVT_H_W|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.h.w", 0, INSN_CLASS_ZFH, "D,s,m", MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
|
||||
{"fcvt.h.wu", 0, INSN_CLASS_ZFH, "D,s", MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.h.wu", 0, INSN_CLASS_ZFH, "D,s,m", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
|
||||
{"fcvt.s.h", 0, INSN_CLASS_ZFH, "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.d.h", 0, INSN_CLASS_D_AND_ZFH, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.q.h", 0, INSN_CLASS_Q_AND_ZFH, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.h.s", 0, INSN_CLASS_ZFH, "D,S", MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.h.s", 0, INSN_CLASS_ZFH, "D,S,m", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
|
||||
{"fcvt.h.d", 0, INSN_CLASS_D_AND_ZFH, "D,S", MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.h.d", 0, INSN_CLASS_D_AND_ZFH, "D,S,m", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 },
|
||||
{"fcvt.h.q", 0, INSN_CLASS_Q_AND_ZFH, "D,S", MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.h.q", 0, INSN_CLASS_Q_AND_ZFH, "D,S,m", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
|
||||
{"fclass.h", 0, INSN_CLASS_ZFH, "d,S", MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
|
||||
{"feq.h", 0, INSN_CLASS_ZFH, "d,S,T", MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
|
||||
{"flt.h", 0, INSN_CLASS_ZFH, "d,S,T", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
|
||||
{"fle.h", 0, INSN_CLASS_ZFH, "d,S,T", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
|
||||
{"fgt.h", 0, INSN_CLASS_ZFH, "d,T,S", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
|
||||
{"fge.h", 0, INSN_CLASS_ZFH, "d,T,S", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
|
||||
{"fmv.x.h", 0, INSN_CLASS_ZFH, "d,S", MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 },
|
||||
{"fmv.h.x", 0, INSN_CLASS_ZFH, "D,s", MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 },
|
||||
{"fcvt.l.h", 64, INSN_CLASS_ZFH, "d,S", MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.l.h", 64, INSN_CLASS_ZFH, "d,S,m", MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 },
|
||||
{"fcvt.lu.h", 64, INSN_CLASS_ZFH, "d,S", MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.lu.h", 64, INSN_CLASS_ZFH, "d,S,m", MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 },
|
||||
{"fcvt.h.l", 64, INSN_CLASS_ZFH, "D,s", MATCH_FCVT_H_L|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.h.l", 64, INSN_CLASS_ZFH, "D,s,m", MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 },
|
||||
{"fcvt.h.lu", 64, INSN_CLASS_ZFH, "D,s", MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
|
||||
{"fcvt.h.lu", 64, INSN_CLASS_ZFH, "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
|
||||
|
||||
/* Single-precision floating-point instruction subset. */
|
||||
{"frcsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
|
||||
{"frsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
|
||||
|
||||
Reference in New Issue
Block a user