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s390-vregs.exp: Fix Tcl error after non-zero-pad patch

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s390-vregs.exp yields a Tcl error:

  ERROR: can't read "i": no such variable
      while executing
  "expr $a_high * ($i + 1) * $a_high "
      (procedure "hex128" line 2)
      invoked from within
  "hex128 $a_high $a_low $b_high $b_low"
  ...

This is a regression, caused by commit 30a254669b16b8 -- "Don't always
zero pad in print_*_chars".  That patch introduced a new procedure
"hex128" for formatting a 128-bit value as hex, but it accidentally moved
the calculation of the 128-bit value into that new procedure as well
instead of leaving it in the original context.  This is fixed.

gdb/testsuite/ChangeLog:

	* gdb.arch/s390-vregs.exp: Calculate parameters to hex128 in the
	calling context.
	(hex128): Drop erroneous calculation of parameters.
This commit is contained in:
Andreas Arnez
2017-07-24 18:35:30 +02:00
parent 7684e58062
commit 031ed05dd2
2 changed files with 16 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
gdb/testsuite/ChangeLog
View File

@ -1,3 +1,9 @@
2017-07-24 Andreas Arnez <arnez@linux.vnet.ibm.com>
* gdb.arch/s390-vregs.exp: Calculate parameters to hex128 in the
calling context.
(hex128): Drop erroneous calculation of parameters.
2017-07-22 Simon Marchi <simon.marchi@ericsson.com> 2017-07-22 Simon Marchi <simon.marchi@ericsson.com>
* gdb.python/py-unwind.exp: Disable stack protection when * gdb.python/py-unwind.exp: Disable stack protection when

18
gdb/testsuite/gdb.arch/s390-vregs.exp
View File

@ -147,14 +147,12 @@ gdb_continue_to_breakpoint "change vrs"
set vregs [capture_command_output "info registers vector" ""] set vregs [capture_command_output "info registers vector" ""]
# Format a 128-bit value, given individual 4-byte values, as hex. # Format a 128-bit value, given individual 4-byte values, as hex.
# Leading zeros are suppressed. # Suppress leading zeros.
proc hex128 {a_high a_low b_high b_low} { proc hex128 {a_high a_low b_high b_low} {
set result [format %08x%08x%08x%08x \ set result [format "%x%08x%08x%08x" $a_high $a_low $b_high $b_low]
[expr $a_high * ($i + 1) * $a_high ] \ regsub -- "^0*" $result "" result
[expr $a_low * ($i + 1) * $a_low ] \ if { $result eq "" } { set result 0 }
[expr $b_high * (32 - $i) * $b_high * 32] \ return $result
[expr $b_low * (32 - $i) * $b_low * 32] ]
return [regsub -- "^0*" $result ""]
} }
set j 1 set j 1
@ -162,7 +160,11 @@ foreach {- r i val} [regexp -all -inline -line \
{^(\D*)(\d+)\s+.*?uint128 = 0x([0-9a-f]+?)} $vregs] { {^(\D*)(\d+)\s+.*?uint128 = 0x([0-9a-f]+?)} $vregs] {
if { $r ne "v" } { if { $r ne "v" } {
fail "info registers vector: bad line $j" fail "info registers vector: bad line $j"
} elseif { $val ne [hex128 $a_high $a_low $b_high $b_low] } { } elseif { $val ne [hex128 \
[expr $a_high * ($i + 1) * $a_high ] \
[expr $a_low * ($i + 1) * $a_low ] \
[expr $b_high * (32 - $i) * $b_high * 32] \
[expr $b_low * (32 - $i) * $b_low * 32] ] } {
fail "compare \$v$i" fail "compare \$v$i"
} }
incr j 1 incr j 1