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PR 10288

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* arm-dis.c (print_insn_coprocessor): Check that a user specified
        ARM architecture supports the matched instruction.
        (print_insn_arm): Likewise.
        (select_arm_features): New function.  Fills in the fields of an
        arm_feature_set structure based on a given arm machine number.
        (print_insn): Initialise an arm_feature_set structure.

        * objdump.c (disassemble_bytes): Set the
        USER_SPECIFIED_MACHINE_TYPE flag in the disassemble_info structure
        if the user has invoked the -m switch.
        * doc/binutils.texi: Document the additional behaviour of
        objdump's -m switch for ARM targets.

        * dis-asm.h (USER_SPECIFIED_MACHINE_TYPE): New value for the flags
        field of struct disassemble_info.

        * gas/arm/align.s: Add labels so that COFF based targets can
        correctly locate THUMB code.
        * gas/arm/copro.d: Do not pass --architecture switch to objdump.
This commit is contained in:
Nick Clifton
2009-06-18 10:31:21 +00:00
parent 470c710ef0
commit 0313a2b8d2
10 changed files with 556 additions and 422 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
binutils/ChangeLog
View File

@ -1,6 +1,16 @@
2009-06-18 Nick Clifton <nickc@redhat.com>
PR 10288
* objdump.c (disassemble_bytes): Set the
USER_SPECIFIED_MACHINE_TYPE flag in the disassemble_info structure
if the user has invoked the -m switch.
* doc/binutils.texi: Document the additional behaviour of
objdump's -m switch for ARM targets.
2009-06-18 Dave Korn <dave.korn.cygwin@gmail.com>
Merge cegcc and mingw32ce target name changes from CeGCC project.
* configure.in: Merge cegcc and mingw32ce target name changes from
CeGCC project.
2007-12-25 Pedro Alves <pedro_alves@portugalmail.pt>

11
binutils/doc/binutils.texi
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@ -1801,6 +1801,10 @@ expected to contain instructions.
Like @option{-d}, but disassemble the contents of all sections, not just
those expected to contain instructions.
If the target is an ARM architecture this switch also has the effect
of forcing the disassembler to decode pieces of data found in code
sections as if they were instructions.
@item --prefix-addresses
When disassembling, print the complete address on each line. This is
the older disassembly format.
@ -1884,6 +1888,13 @@ can be useful when disassembling object files which do not describe
architecture information, such as S-records. You can list the available
architectures with the @option{-i} option.
If the target is an ARM architecture then this switch has an
additional effect. It restricts the disassembly to only those
instructions supported by the architecture specified by @var{machine}.
If it is necessary to use this switch because the input file does not
contain any architecture information, but it is also desired to
disassemble all the instructions use @option{-marm}.
@item -M @var{options}
@itemx --disassembler-options=@var{options}
Pass target specific information to the disassembler. Only supported on

2
binutils/objdump.c
View File

@ -1526,6 +1526,8 @@ disassemble_bytes (struct disassemble_info * info,
info->bytes_per_line = 0;
info->bytes_per_chunk = 0;
info->flags = disassemble_all ? DISASSEMBLE_DATA : 0;
if (machine)
info->flags |= USER_SPECIFIED_MACHINE_TYPE;
if (info->disassembler_needs_relocs
&& (bfd_get_file_flags (aux->abfd) & EXEC_P) == 0

7
gas/testsuite/ChangeLog
View File

@ -1,3 +1,10 @@
2009-06-18 Nick Clifton <nickc@redhat.com>
PR 10288
* gas/arm/align.s: Add labels so that COFF based targets can
correctly locate THUMB code.
* gas/arm/copro.d: Do not pass --architecture switch to objdump.
2009-06-15 Nick Clifton <nickc@redhat.com>
PR gas/10186

4
gas/testsuite/gas/arm/align.s
View File

@ -1,5 +1,7 @@
.syntax unified
.thumb
.global foo
foo:
nop
mov r1,r2
.p2align 4
@ -7,6 +9,8 @@
.p2align 3
.arm
.global bar
bar:
nop
mov r1,r2
.p2align 4

2
gas/testsuite/gas/arm/copro.d
View File

@ -1,4 +1,4 @@
#objdump: -dr --prefix-addresses --show-raw-insn --architecture=armv5te
#objdump: -dr --prefix-addresses --show-raw-insn
#name: ARM CoProcessor Instructions
#as: -march=armv5te -EL

9
include/ChangeLog
View File

@ -1,11 +1,16 @@
2009-06-18 Nick Clifton <nickc@redhat.com>
* dis-asm.h (USER_SPECIFIED_MACHINE_TYPE): New value for the flags
field of struct disassemble_info.
2009-06-09 Ian Lance Taylor <ian@airs.com>
* ansidecl.h (ATTRIBUTE_UNUSED_LABEL): Define for C++.
2009-06-15 Nick Clifton <nickc@redhat.com>
* dis-asm.h (struct disassemble_info): New value for the flags
field.
* dis-asm.h (DISASSEMBLE_DATA): New value for the flags field of
struct disassemble_info.
2009-06-02 Ian Lance Taylor <iant@google.com>

3
include/dis-asm.h
View File

@ -113,6 +113,9 @@ typedef struct disassemble_info
#define INSN_HAS_RELOC (1 << 31)
/* Set if the user has requested the disassembly of data as well as code. */
#define DISASSEMBLE_DATA (1 << 30)
/* Set if the user has specifically set the machine type encoded in the
mach field of this structure. */
#define USER_SPECIFIED_MACHINE_TYPE (1 << 29)
/* Use internally by the target specific disassembly code. */
void *private_data;

10
opcodes/ChangeLog
View File

@ -1,3 +1,13 @@
2009-06-18 Nick Clifton <nickc@redhat.com>
PR 10288
* arm-dis.c (print_insn_coprocessor): Check that a user specified
ARM architecture supports the matched instruction.
(print_insn_arm): Likewise.
(select_arm_features): New function. Fills in the fields of an
arm_feature_set structure based on a given arm machine number.
(print_insn): Initialise an arm_feature_set structure.
2009-06-16 Maciej W. Rozycki <macro@linux-mips.org>
* vax-dis.c (is_function_entry): Return success for synthetic

106
opcodes/arm-dis.c
View File

@ -1635,6 +1635,8 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
for (insn = coprocessor_opcodes; insn->assembler; insn++)
{
const char *c;
if (insn->value == FIRST_IWMMXT_INSN
&& info->mach != bfd_mach_arm_XScale
&& info->mach != bfd_mach_arm_iWMMXt
@ -1671,9 +1673,12 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
cond = 16;
}
}
if ((given & mask) == value)
{
const char *c;
if ((given & mask) != value)
continue;
if ((insn->arch & ((arm_feature_set *) info->private_data)->coproc) == 0)
continue;
for (c = insn->assembler; *c; c++)
{
@ -1815,6 +1820,7 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
break;
}
break;
case 'Q':
switch (given & 0x00408000)
{
@ -1832,6 +1838,7 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
break;
}
break;
case 'R':
switch (given & 0x60)
{
@ -2066,7 +2073,6 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
switch (puw_bits)
{
case 1:
/* fall through */
case 3:
func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
if (imm4)
@ -2074,11 +2080,8 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
break;
case 4:
/* fall through */
case 5:
/* fall through */
case 6:
/* fall through */
case 7:
func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
if (imm4 > 0)
@ -2112,7 +2115,6 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
}
return TRUE;
}
}
return FALSE;
}
@ -2221,7 +2223,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
{
if ((given & 0xef000000) == 0xef000000)
{
/* move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
/* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
unsigned long bit28 = given & (1 << 28);
given &= 0x00ffffff;
@ -2687,13 +2689,18 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
&& info->mach != bfd_mach_arm_iWMMXt)
insn = insn + IWMMXT_INSN_COUNT;
if ((given & insn->mask) == insn->value
if ((given & insn->mask) != insn->value)
continue;
if ((insn->arch & ((arm_feature_set *) info->private_data)->core) == 0)
continue;
/* Special case: an instruction with all bits set in the condition field
(0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
or by the catchall at the end of the table. */
&& ((given & 0xF0000000) != 0xF0000000
if ((given & 0xF0000000) != 0xF0000000
|| (insn->mask & 0xF0000000) == 0xF0000000
|| (insn->mask == 0 && insn->value == 0)))
|| (insn->mask == 0 && insn->value == 0))
{
const char *c;
@ -3967,6 +3974,47 @@ get_sym_code_type (struct disassemble_info *info, int n,
return FALSE;
}
/* Given a bfd_mach_arm_XXX value, this function fills in the fields
of the supplied arm_feature_set structure with bitmasks indicating
the support base architectures and coprocessor extensions.
FIXME: This could more efficiently implemented as a constant array,
although it would also be less robust. */
static void
select_arm_features (unsigned long mach,
arm_feature_set * features)
{
#undef ARM_FEATURE
#define ARM_FEATURE(ARCH,CEXT) \
features->core = (ARCH); \
features->coproc = (CEXT) | FPU_FPA; \
return
switch (mach)
{
case bfd_mach_arm_2: ARM_ARCH_V2;
case bfd_mach_arm_2a: ARM_ARCH_V2S;
case bfd_mach_arm_3: ARM_ARCH_V3;
case bfd_mach_arm_3M: ARM_ARCH_V3M;
case bfd_mach_arm_4: ARM_ARCH_V4;
case bfd_mach_arm_4T: ARM_ARCH_V4T;
case bfd_mach_arm_5: ARM_ARCH_V5;
case bfd_mach_arm_5T: ARM_ARCH_V5T;
case bfd_mach_arm_5TE: ARM_ARCH_V5TE;
case bfd_mach_arm_XScale: ARM_ARCH_XSCALE;
case bfd_mach_arm_ep9312: ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK | FPU_MAVERICK);
case bfd_mach_arm_iWMMXt: ARM_ARCH_IWMMXT;
case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2;
/* If the machine type is unknown allow all
architecture types and all extensions. */
case bfd_mach_arm_unknown: ARM_FEATURE (-1UL, -1UL);
default:
abort ();
}
}
/* NOTE: There are no checks in these routines that
the relevant number of data bytes exist. */
@ -3991,6 +4039,40 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
info->disassembler_options = NULL;
}
/* PR 10288: Control which instructions will be disassembled. */
if (info->private_data == NULL)
{
static arm_feature_set features;
if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
/* If the user did not use the -m command line switch then default to
disassembling all types of ARM instruction.
The info->mach value has to be ignored as this will be based on
the default archictecture for the target and/or hints in the notes
section, but it will never be greater than the current largest arm
machine value (iWMMXt2), which is only equivalent to the V5TE
architecture. ARM architectures have advanced beyond the machine
value encoding, and these newer architectures would be ignored if
the machine value was used.
Ie the -m switch is used to restrict which instructions will be
disassembled. If it is necessary to use the -m switch to tell
objdump that an ARM binary is being disassembled, eg because the
input is a raw binary file, but it is also desired to disassemble
all ARM instructions then use "-marm". This will select the
"unknown" arm architecture which is compatible with any ARM
instruction. */
info->mach = bfd_mach_arm_unknown;
/* Compute the architecture bitmask from the machine number.
Note: This assumes that the machine number will not change
during disassembly.... */
select_arm_features (info->mach, & features);
info->private_data = & features;
}
/* Decide if our code is going to be little-endian, despite what the
function argument might say. */
little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);