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https://github.com/espressif/binutils-gdb.git
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2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-dis.c (print_insn_s390): Pick instruction with most specific mask. * s390-opc.c: Add unused bits to the insn mask. * s390-opc.txt: Reorder some instructions to prefer more recent versions. 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/esa-g5.d: Adjust serveral instructions. * gas/s390/esa-reloc.d: Likewise. * gas/s390/esa-z990.d: Likewise. * gas/s390/zarch-reloc.d: Likewise. * gas/s390/zarch-z10.d: Likewise. * gas/s390/zarch-z9-ec.d: Likewise. * gas/s390/zarch-z900.d: Likewise. 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * ld-s390/tlsbin.dd: bcr 0,%r7 -> nopr %r7. * ld-s390/tlsbin_64.dd: Likewise. * ld-s390/tlspic.dd: Likewise. * ld-s390/tlspic_64.dd: Likewise.
This commit is contained in:
Andreas Krebbel
@ -1,3 +1,11 @@
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2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
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* s390-dis.c (print_insn_s390): Pick instruction with most
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specific mask.
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* s390-opc.c: Add unused bits to the insn mask.
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* s390-opc.txt: Reorder some instructions to prefer more recent
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versions.
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2010-09-27 Tejas Belagod <tejas.belagod@arm.com>
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* arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
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@ -166,6 +166,8 @@ print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info)
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if (status == 0)
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{
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const struct s390_opcode *op;
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/* Find the first match in the opcode table. */
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opcode_end = s390_opcodes + s390_num_opcodes;
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for (opcode = s390_opcodes + opc_index[(int) buffer[0]];
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@ -178,6 +180,7 @@ print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info)
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/* Check architecture. */
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if (!(opcode->modes & current_arch_mask))
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continue;
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/* Check signature of the opcode. */
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if ((buffer[1] & opcode->mask[1]) != opcode->opcode[1]
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|| (buffer[2] & opcode->mask[2]) != opcode->opcode[2]
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@ -186,6 +189,28 @@ print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info)
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|| (buffer[5] & opcode->mask[5]) != opcode->opcode[5])
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continue;
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/* Advance to an opcode with a more specific mask. */
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for (op = opcode + 1; op < opcode_end; op++)
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{
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if ((buffer[0] & op->mask[0]) != op->opcode[0])
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break;
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if ((buffer[1] & op->mask[1]) != op->opcode[1]
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|| (buffer[2] & op->mask[2]) != op->opcode[2]
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|| (buffer[3] & op->mask[3]) != op->opcode[3]
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|| (buffer[4] & op->mask[4]) != op->opcode[4]
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|| (buffer[5] & op->mask[5]) != op->opcode[5])
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continue;
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if (((int)opcode->mask[0] + opcode->mask[1] +
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opcode->mask[2] + opcode->mask[3] +
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opcode->mask[4] + opcode->mask[5]) <
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((int)op->mask[0] + op->mask[1] +
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op->mask[2] + op->mask[3] +
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op->mask[4] + op->mask[5]))
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opcode = op;
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}
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/* The instruction is valid. */
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if (opcode->operands[0] != 0)
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(*info->fprintf_func) (info->stream, "%s\t", opcode->name);
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@ -398,10 +398,10 @@ const struct s390_operand s390_operands[] =
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#define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
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#define MASK_RRS_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
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#define MASK_RRS_RRRD0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
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#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RSL_R0RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
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#define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
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#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
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#define MASK_RSL_R0RD { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
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#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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@ -412,10 +412,10 @@ const struct s390_operand s390_operands[] =
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#define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
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#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
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#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
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#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
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#define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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#define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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@ -107,10 +107,10 @@ b7 lctl RS_CCRD "load control" g5 esa,zarch
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82 lpsw S_RD "load PSW" g5 esa,zarch
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18 lr RR_RR "load" g5 esa,zarch
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b1 lra RX_RRRD "load real address" g5 esa,zarch
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25 lrdr RR_FF "load rounded (ext. to long)" g5 esa,zarch
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35 lrer RR_FF "load rounded (long to short)" g5 esa,zarch
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25 ldxr RR_FF "load rounded (ext. to long)" g5 esa,zarch
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25 lrdr RR_FF "load rounded (ext. to long)" g5 esa,zarch
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35 ledr RR_FF "load rounded (long to short)" g5 esa,zarch
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35 lrer RR_FF "load rounded (long to short)" g5 esa,zarch
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22 ltdr RR_FF "load and test (long)" g5 esa,zarch
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32 lter RR_FF "load and test (short)" g5 esa,zarch
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12 ltr RR_RR "load and test" g5 esa,zarch
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@ -119,10 +119,10 @@ b24b lura RRE_RR "load using real address" g5 esa,zarch
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af mc SI_URD "monitor call" g5 esa,zarch
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6c md RX_FRRD "multiply (long)" g5 esa,zarch
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2c mdr RR_FF "multiply (long)" g5 esa,zarch
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7c me RX_FRRD "multiply (short to long)" g5 esa,zarch
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7c mde RX_FRRD "multiply (short to long)" g5 esa,zarch
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3c mer RR_FF "multiply (short to long)" g5 esa,zarch
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7c me RX_FRRD "multiply (short to long)" g5 esa,zarch
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3c mder RR_FF "multiply short to long hfp" g5 esa,zarch
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3c mer RR_FF "multiply (short to long)" g5 esa,zarch
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4c mh RX_RRRD "multiply halfword" g5 esa,zarch
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fc mp SS_LLRDRD "multiply decimal" g5 esa,zarch
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1c mr RR_RR "multiply" g5 esa,zarch
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@ -259,7 +259,9 @@ a8 mvcle RS_RRRD "move long extended" g5 esa,zarch
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a70c mhi RI_RI "multiply halfword immediate" g5 esa,zarch
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b252 msr RRE_RR "multiply single" g5 esa,zarch
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71 ms RX_RRRD "multiply single" g5 esa,zarch
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a700 tmlh RI_RU "test under mask low high" g5 esa,zarch
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a700 tmh RI_RU "test under mask high" g5 esa,zarch
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a701 tmll RI_RU "test under mask low low" g5 esa,zarch
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a701 tml RI_RU "test under mask low" g5 esa,zarch
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0700 nopr RR_0R_OPT "no operation" g5 esa,zarch
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0700 b*8r RR_0R "conditional branch" g5 esa,zarch
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@ -366,8 +368,6 @@ b277 rp S_RD "resume program" g5 esa,zarch
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b27d stsi S_RD "store system information" g5 esa,zarch
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01ff trap2 E "trap" g5 esa,zarch
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b2ff trap4 S_RD "trap4" g5 esa,zarch
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a700 tmlh RI_RU "test under mask low high" g5 esa,zarch
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a701 tmll RI_RU "test under mask low low" g5 esa,zarch
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b278 stcke S_RD "store clock extended" g5 esa,zarch
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b2a5 tre RRE_RR "translate extended" g5 esa,zarch
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eb000000008e mvclu RSE_RRRD "move long unicode" g5 esa,zarch
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